ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–43
9.3.7.2 Start/Stop Operations by Event Trigger
Here is the setting used to control the counter by event triggers.
1) FTnTRG0 setting
Enable/Disable counter start/stop by event triggers
Set whether or not to clear the counter at stop by an event trigger
Set whether or not to accept the next counter start after stop by an event trigger
Set the event trigger source (EXI0-7TGO, TIMER0-7INT, FTM0-3TGO)
2) FTnTRG1 setting
Set the edge of the event trigger which generates counter start
Set the edge of the event trigger which generates counter stop
3) Controlling FTnCON0
Set FTnTGEN to "1" to enter the waiting state for event triggers.
Then, set FTnRUN to "1" to start the counter by the software.
Set FTnRUN to "0" during the counter operation to stop the counter by the software.
Because the trigger signal is sampled at FTnCK when the external input (EXInTGO) is selected as counter
control by event triggers, the input pulse width should be set to Analog filter 200ns and three or more sampling
clocks. Pulses shorter than three sampling clock may be or may not be removed. Note that the sampling is not
performed when the timer interrupt is selected as the event trigger.
Figure 9-8 shows the sampling timing of the external input.
Figure 9-8 Sampling Timing of External Input
FTnCK
External input pin
Sampling clock
Waveform after the sampling
FTMn accepts external input
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...