ML620Q503/Q504 User's Manual
Chapter 13 UART
FEUL620Q504
13–14
13.3.4
Transmit Operation
Transmission is started by setting the U0EN bit of the UART0 control register (UA0CON) to "1" and set transfer
data to UA1BUF. The order of UA0EN setting and UA1BUF setting does not matter.
Figure 13-5 shows the operation timing for transmission.
When the U0EN bit is set to "1" (
), the baud rate generator generates an internal transfer clock of the baud rate
set and starts transmit operation.
The start bit is output to the TXD pin by the falling edge of the internal transfer clock (
). Subsequently, the
transmitted data, a parity bit, and a stop bit are output.
When the start bit is output (
), a UART0 interrupt is requested. In the UART0 interrupt routine, the next data
to be transmitted is written to the transmit buffer (UA1BUF).
When the next data to be transmitted is written to the transmit buffer (UA1BUF), the transmit buffer status flag
(U1FUL) is set to "1" (
) and a UART transmission interrupt is requested on the falling edge of the internal
transfer clock (
) after transmission of the stop bit. At this time if the UART transmission interrupt routine is
terminated without writing the next data to the transmit buffer, the U1FUL bit is not set to "1" (
). The transmit
operation stops when the stop bit is sent, the U1EN bit is reset to "0", and the UART transmission interrupt is
requested.
The valid period for the next transmit data to be written to the transmit buffer is from the generation of an
interrupt to the termination of stop bit transmission. (
)
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...