Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–22
9.2.13 FTMn Interrupt Enable Register (FTnINTE: n = 0,1,2,3)
Address: 0F418H(FT0INTEL/FT0INTE), 0F419H(FT0INTEH),
0F438H(FT1INTEL/FT1INTE), 0F439H(FT1INTEH),
0F458H(FT2INTEL/FT2INTE), 0F459H(FT2INTEH),
0F478H(FT3INTEL/FT3INTE), 0F479H(FT3INTEH)
Access: R/W
Access size: 8/16 bit
Initial value: 0000H
7 6 5 4 3 2 1 0
FTnINTEL – – – FTnIETR FTnIETS FTnIEB FTnIEA FTnIEP
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
FTnINTEH – – – – – FTnIOB FTnIOA FTnIOP
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
FTnINTE is a special function register (SFR) used to control the interrupt of FTMn.
Setting a bit of FTnINTE to
" 1 " makes the interrupt enabled and notifies the interrupt controller.
Description of Bits
•
FTnIEP (bit 0)
Sets the period interrupt enable of FTMn.
FTnMD FTnIEP Description
TIMER
CAPTURE
PWM1/2
0 Period interrupt disabled (initial value)
1 Period interrupt enabled
•
FTnIEA (bit 1)
Sets the event timing A interrupt enable of FTMn.
FTnMD FTnIEA Description
TIMER
PWM1/2
0 Event timing A interrupt disabled (initial value)
1 Event timing A interrupt enabled
CAPTURE
0 Capture A interrupt disabled
1 Capture A interrupt enabled
•
FTnIEB (bit 2)
Sets the event timing B interrupt enable of FTMn.
FTnMD FTnIEB Description
TIMER
PWM1/2
0 Event timing B interrupt disabled (initial value)
1 Event timing B interrupt enabled
PMW2
0 Set FTnIEB to 0 in this mode.
1 Prohibited in this mode.
CAPTURE
0 Capture B interrupt disabled
1 Capture B interrupt enabled