Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 28 Voltage Level Supervisor
FEUL620Q504 28-10
Figure 28-4 shows an example of the operation timing diagram when detecting without sampling and setting the
VLS interrupt issue.
①
Set ENVLS to “1” from the CPU to turn on the VLS.
②
When the VLS analog output is stabilized, the ready flag (VLSRF) is set to ”1”.
③
The voltage level detection flag (VLSF) is set to “1” to issue a VLS interrupt because V
DD
becomes lower than
the specified threshold voltage (V
VLS
).
④
The voltage level detection flag (VLSF) is set to “0” because V
DD
becomes higher than the
threshold voltage of rise (V
VLS
+H
VLS
).
⑤
Set ENVLS to “0” from the CPU to turn off the VLS.
Figure 28-4 Operation Timing Diagram When Detecting without Sampling
and Setting VLS Interrupt Issue
①
Stabilization
time
ENVLS
Threshold voltage
V
VLS
VLS analog output
V
SS
V
DD
Ready flag: VLSRF
↓
↓
↓ ↓
Detection flag: VLSF
VLS interrupt
(rise)
(fall)
V
VLS+
H
VLS
② ③ ④ ⑤
↓