ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-9
4.2.6 Block Control Register 45 (BLKCON45)
Address: 0F06CH
Access: R/W
Access size: 8/16 bit
Initial value: 0400H
7
6
5
4
3
2
1
0
BLKCON4
–
–
–
–
–
–
DRAD
DSAD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
BLKCON5
–
–
–
–
–
DLLD
DVLS
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
1
0
0
BLKCON45 is a special function register (SFR) to control each block operation.
Description of Bits
•
DSAD
(bit 0)
The DSAD bit is used to control the successive approximation type (SA type) A/D converter operation.
DSAD
Description
0
Enable operating the SA type A/D converter (initial value)
1
Disable operating the SA type A/D converter
•
DRAD
(bit 1)
The DRAD bit is used to control the RC oscillation type A/D converter operation.
DRAD
Description
0
Enable operating the RC oscillation type A/D converter (initial value)
1
Disable operating the RC oscillation type A/D converter
•
DVLS
(bit 9)
The DVLS bit is used to control the operation of the power supply voltage detection circuit (VLS).
DVLS
Description
0
Enable operating VLS (initial value)
1
Disable operating VLS
•
DLLD
(bit 10)
The DLLD bit is used to control the operation of the power supply voltage dropping detection circuit
(LLD).
DLLD
Description
0
Enable operating LLD
1
Disable operating LLD (initial value)
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...