ML620Q503/Q504 User's Manual
Chapter 27
Flash Memory Control
FEUL620Q504 27-
12
27.3.4 Boot Area Remap Function by Software
This function can remap the area from 0000H to 0FFFH (4 KB) to the area of the same size (4 KB) starting from
the address set in the REMAPADD register.
The program can start from the remapped area by setting the start address of the area to remap in the
REMAPADD register and performing the software reset (* only CPU is reset) by execution of the BRK
instruction. For the BRK instruction, refer to "nX-U16/100 Core Instruction Manual".
The remap function also remaps the vector table areas (reset vector area, hardware interrupt vector area, and
software interrupt vector area). It is feasible to manage interrupts independently by the program in the remap area.
If the program size is 4 KB or less, it is feasible to develop the program independently of the main program. This
is suitable for the cases that want to control interrupts such as the self-rewrite program separately from the normal
interrupt.
Figure 27-2 shows a sample program for remap (when the start address of the remap area is F000H). Figure 27-3
shows the memory map before and after remapping.
MOV
R0,
#00FH
;
ST
R0,
0F0ECH
; Set the higher 4 bits of the start address of the area
; to remap to the REMAPADD register (0F0ECH).
MOV
PSW, #02H
; Set the interrupt level (ELEVEL) to 2.
BRK
; Execute the BRK instruction.
; Execution starts with the code at the remapped F000H.
Figure 27-2 Sample Program for Remap
Figure 27-3 Memory Map before/after Remapping
[Note]
If the area 0:0000H to 0:1000H (4KB) before remapping need to be read after remapping, read it from 8th
segment. If the area 0:0000H to 0:1000H (4KB) before remapping need to be written, set the address
(0:0000H to 0:1000H) that was used before remapping to the flash address register (FLASHA). For FLASHA,
refer to "27.2.2 Flash Address Register (FLASHA)".
0:0000H
Normal boot area
4KB
Test area
Program area
0:FC00H
0:0000H
Program area
Before remapping
After remapping
0:F000H
Program area
Remap
0:1000H
0:1000H
Test area* 1 KB
Program area
3KB
0:FC00H
0:F000H
Test area 1 KB
Program area
3KB
* The test area cannot be used as program area.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...