Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 6 Clock Generation Circuit
FEUL620Q504 6–23
6.3.2.6 High-Speed External Clock Mode Operation
For the high-speed external clock, the oscillation start/stop can be controlled by the frequency control register1
(FCON1).
Oscillation can be started by setting the ENOSC bit of FCON1 to "1". The external clock starts to be supplied as
OSCLK after the built-in RC oscillation clock is counted to 512 after the oscillation starts and then the external
clock is counted to 128. The high-speed clock generation circuit stops oscillation when it shifts to the STOP
mode by software. By releasing the stop mode by an external interrupt, the low-speed built-in RC oscillation
clock is counted to 29 and then the high-speed built-in RC oscillation clock is counted to 512, then the built-in
RC oscillation clock is supplied as OSCLK. And OSCLK changes from RC oscillation into external clock by the
automatic operation in case of 128 counts by the external clock.
Refer to Chapter 4 “Power Management” for the operation at each power down mode.
Figure 6-14 shows the operation waveforms of the high-speed clock generation circuit in the external clock input
mode.
ENOSC bit
External interrupt occurred
OSCLK switch
OSCLK
High-speed oscillation
128 counts
RC oscillation
STOP
mode
built-in RC oscillation
RC oscillation
High-speed
built-in RC oscillation
High-speed
External clock
HOSCS bit
RC oscillation 512 counts
Low-speed oscillation
built-in oscillation
Low-speed RC oscillation 29 counts
OSCM=”11”
External clock
External clock
built-in oscillation
High-speed oscillation
128 counts
built-in RC oscillation
RC oscillation 512 counts
OSCLK switch
(a) In the low-speed built-in RC oscillation mode
External clock External clock