Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-14
14.2.7 UARTF0 Clock Adjustment Register (UAF0CAJ)
Address: 0F7CAH
Access: R/W
Access size: 8/16 bits
Initial value: 000DH
7 6 5 4 3 2 1 0
UAF0CAJL – – – UF0CAJ4 UF0CAJ3 UF0CAJ2 UF0CAJ1 UF0CAJ0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 1 1 0 1
15 14 13 12 11 10 9 8
UAF0CAJH – – – – – – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
UAF0CAJ is a special function register (SFR) used to adjust the base clock for the baud rate clock of UARTF0.
Description of Bits
•
UF0CAJ4-0 (bits 4 to 0)
Adjusts the base clock for the baud rate clock of UARTF0.
Each setting of different clocks of SYSCLK is as below.
SYSCLK UF0CAJ4 UF0CAJ3 UF0CAJ2 UF0CAJ1 UF0CAJ0
16.000MHz
0 1 1 0 1 8.000MHz
4.000MHz
8.192MHz
0 1 0 1 0
4.096MHz
[Note]
When using UARTF0, always set SYSCLK to 4MHz or more. If SYSCLK is 4MHz or less, it does not
work normally.
For details, see 0 "Baud rate clock generation".