Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–31
5.2.14 Interrupt Level Control Register 3 (ILC3)
Address: 0F028H
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7 6 5 4 3 2 1 0
ILC3L – – – – – – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
ILC3H L1MD0 L0MD0 L1VLS L0VLS L1LOSC L0LOSC – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
The interrupt level control register 3 is a special function register (SFR) used to set the level of the interrupt
source enabled by IE3.
Write access to this register is possible only when the interrupt level control is enabled by the ILEN register.
Level 1 to 4 can be set for each interrupt source. The register which has the higher level is given the higher
priority.
Description of Bits
•
L1-0LOSC (bits 11 to 10)
L1-0LOSC set the level of the OSC interrupt (LOSCINT).
L1LOSC L0LOSC Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0VLS (bits 13 to 12)
L1-0VLS set the level of the VLS interrupt (VLSINT).
L1VLS L0VLS Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0MD0 (bits 15 to 14)
L1-0MD0 set the level of the melody 0 interrupt (MD0INT).
L1MD0 L0MD0 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4