Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 8 Timers
FEUL620Q504 8–11
8.3 Description of operation
8.3.1 Normal timer mode operation
When the TnRUN bit of timer n register0(TMSTR0) are set to 1, The timer counters(TMnC) is in operation
state(TnSTAT =”1”) by the first falling edge of the timer clock(TnCK) that are selected by the Timer control
register(TMnCON), and start count up by the second falling edge.
When the count value of TMnC coincide with the timer data register (TMnD), timer interrupt (TMnINT) occurs
on the next falling edge of timer clock, at same time TMnC are reset to “00H” and continues incremental count.
When the TnSTP bits are set to “1”, TMnC stop a count after one fall count of the timer clock (TnCK) , and
TnSTAT bit of timer status register 0(TMSTAT0) becomes “0”.
When the TnRUN bits are set to “1” again, TMn restart an incremental count from the previous values. To
initialize TMnC to “00H”, perform write operation in TMnC.
The timer interrupt period (T
TMI
) is expressed by the following equation.
T
TMI
=
TMnD + 1
(n=0
～
7)
TnCK (Hz)
TMnD: Timer 0 to 7 data register (TMnD) setting value (01H to 0FFH)
TnCK: Clock frequency selected by the Timer 0 to 7 control register 0 (TMnCON)
After TnRUN bit are set to "1", timer counter are synchronized by the timer clock and counting starts so that an
error of a maximum of 1 clock period occurs until the first timer interrupt. The timer interrupt periods from the
second time are constant.
Figure 8-2 shows the normal timer mode operation timing diagram of Timer 0 to 7
Figure 8-2 Normal Timer Mode Operation Timing Diagram of Timer 0 to 7
[Note]
Count stop and Timer interrupt may occur at same time because Counter stop operation is performed
synchronizing with count operation.
TMnC
XX
00
88
TMnD
TMnINT
TnSTAT
Write TMnC
TnCK
TnRUN
01
02
87
88 00
62 5F 60
61
01
88 88
(n=0 to 7)
T
TMI
TnSTP
T
TMI