ML620Q503/Q504 User's Manual
Chapter 27
Flash Memory Control
FEUL620Q504 27-
15
27.3.7 Sample Program
This section lists sample programs for block erase/sector erase/1-word write (assuming that the flash segment
register is already set).
(1) Block erase/sector erase
LEA
offset FLASHAH
; EA
←FLASHAH address
MOV
R0,
#0FAH
; Flash acceptor enable data
MOV
R1,
#0F5H
; Flash acceptor enable data
MOV
R2,
#01H (#02H)
; Block (sector) erase setting data
MOV
R4,
#(offset FLASHACP)&0FFH
MOV
R5,
#(offset FLASHACP)>>8
; ER4
←FLASHACP address
MOV
R6,
#(offset FLASHCON)&0FFH
MOV
R7,
#(offset FLASHCON)>>8
; ER6
←FLASHCON address
:
(Set the erase start block address in R9)
MARK:
SB
FSELF
; Enable flash write/erase
LOOP:
ST
R0,
[ER4]
; Enable flash acceptor
ST
R1,
[ER4]
; Enable flash acceptor
ST
R9,
[EA]
; Set block (sector) address
ST
R2,
[ER6]
; Start block (sector) erase
NOP
;
∗
Always set
NOP
;
∗
Always set
RB
FSELF
; Disable flash write/erase
(2) 1-word write
LEA
offset FLASHAH
; EA←FLASHAH address
MOV
R0,
#0FAH
; Flash acceptor enable data
MOV
R1,
#0F5H
; Flash acceptor enable data
MOV
R2,
#02H
; Address increment data
MOV
R3,
#00H
MOV
R4,
#(offset FLASHACP)&0FFH
MOV
R5,
#(offset FLASHACP)>>8
; ER4
←FLASHACP address
:
(Set the write start address in ER8)
(Set the write end address in ER12)
MARK:
SB
FSELF
; Enable flash write/erase
ST
R0,
[ER4]
; Enable flash acceptor
ST
R1,
[ER4]
; Enable flash acceptor
ST
XR8,
[EA]
; Set address and data, start 1-word write
NOP
;
∗
Always set
NOP
;
∗
Always set
L
ER14,
[ER8]
; Load data
CMP
ER14,
ER10
; Check data
BNE
ERROR
; Go to error routine on error
ADD
ER8,
ER2
; Address increment
CMP
ER8,
ER12
BLE
MARK
; Compare addresses
RB
FSELF
; Disable flash write/erase
Figure 27-6 Sample Programs for Write/Erase
[Note]
• Data erase/write during the program operation may cause the malfunction of program. Write to an address
unrelated to the operation of the program.
• Be sure to set the NOP instruction twice or more, following the block erase start instruction or the write to
FLASHD instruction.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...