Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 10 Watchdog Timer
FEUL620Q504 10–5
10.3 Description of Operation
The WDT counter starts counting after the system reset has been released and the low-speed clock(LSCLK) oscillation
start.
Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" when
WDP is "1".
WDP is reset to “0” at the time of system reset or when the WDT counter overflows and is inverted whenever data is
written to WDTCON.
When the WDT counter cannot be cleared within the WDT counter overflow period (TWOV), a watchdog timer
interrupt (WDTINT) occurs. If the WDT counter is not cleared even by the software processing performed following
the watchdog timer interrupt and overflow occurs again, WDT reset occurs and the mode shifts to a system reset mode.
For the overflow period TWOV) of the WDT counter, one of 125ms, 500ms, 2s, and 8s can be selected by the
watchdog mode register (WDTMOD).
Clear the WDT counter within the clear period of the WDT counter shown in Table 10-1.
Table 10-1 Clear Period of WDT Counter
WDT1 WDT0 T
WOV
T
WCL
0 0 4096 counts at LSCLK (125 ms*) 3968 counts at LSCLK (Approx. 121 ms*)
0 1 16384 counts at LSCLK (500 ms*) 16256 counts at LSCLK (Approx. 496 ms*)
1 0 65536 counts at LSCLK (2000 ms*) 65408 counts at LSCLK (Approx. 1996 ms*)
1 1 262144 counts at LSCLK (8000 ms*) 262016 count at LSCLK (Approx. 7996 ms*)
*: where LSCLK = 32.768kHz. T
WOV
and T
WCL
depends on a frequency of the LSCLK.
[Note]
WDT counter clock is T256HZ that is divided by 128 of LSCLK. Therfor, keep on supply the LSCLK during not reset
and STOP-mode conditions.
・
The time of Table 10-1 is changed with the frequency of the LSCLK to be used. It is calculable by the frequency of
low speed crystal oscillator to be used as follows.
Ex)Operate by LSCLK=32.768kHz (set WDT1/WDT0=00)
T
WOV
: 1 / ((32.768[kHz]) / 128 [dividing]) * 32 [clock] = 125 [msec]