Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

Page: 171 / 553

ML620Q503/Q504 User’s Manual
Chapter 8 Timers
FEUL620Q504 8–1
8. Timers
8.1 Overview
This LSI includes 8 channels of 8-bit timers. A pair of 2 timers functions as 16-bit timer.
8.1.1 Features
•
The timer interrupt (TMnINT, n=0 to 7) is generated when the values of timer counter register (TMnC, n=0 to7) and
timer data register (TMnD, n=0 to 7) coincide.
•
A timer configured by combining timer 0 and timer 1 or timer 2 and timer 3 or timer 4 and timer 5 or timer 6 and
timer 7 can be used as a 16-bit timer.
•
low-speed clock(LSCLK), high-speed clock(OSCLK), and external input(P42/P43/P52/P53) are selectable as timer
clock(selectable clock is different every channel).
•
Timer clock can be divided by 1, 2, 4, 8, 16, 32, and 64 by divider function.
8.1.2 Configuration
Figure 8-1 shows the configuration of the timers.
(a) In 8-bit Timer Mode (Timers 0 to 7)
(b) 16-bit Timer Mode (Timers 0 to 7)
TMnCON: Timer control register TMSTR0: Timer start register 0
TMmD, TMnD: Timer data registers TMSTP0: Timer stop register 0
TMmC, TMnC: Timer counter registers TMSTAT0: Timer status register 0
Figure 8-1 Configuration of Timers
TMnC
8
Data bus
TMnINT
LSCLK
TMnCON
TMSTR0
TMSTP0
TMSTAT0
R
Match
TMnD
Comparator
8
OSCLK
8
n = 0 to 7
Write TMnC
TnCK
8
External clock
TMnC
TMmINT
LSCLK
TMnCON
TMSTR0
TMSTP0
TMSTAT0
R
Match
Comparator
OSCLK
n = 0,2,4,6
m = n+1
Write TMmC
TnCK
Write TMnC
TMnD TMmD TMmC
R
8
8
16
8 8
16
External clock
Data bus
8 8
8 8