Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–58
5.3.6 Interrupt Processing When Interrupt Level Control Enabled
(1) Interrupt processing
The interrupt handler carries out the following processing.
i. The following processing is made when multiple interrupts are enabled.
When a higher level interrupt request occurs, that request should be processed with priority. For this reason,
the general-purpose registers are saved to memory and the EPW and EPSW registers are pushed in order to
retain the processor state at return.
ii. When multiple interrupts are ready to be processed, the EI instruction is executed to enable the processor
interrupt.
(2) Return from interrupt
The interrupt handler carries out the following processing.
i. After the desired processing is completed by the interrupt, the processor interrupt is disabled.
ii. A write access is made to the current interrupt request level register (CIL) to clear the highest current interrupt
request level.
iii. If the interrupt is in the highest level, the general-purpose registers are restored from memory, and the RTI
instruction is executed to return from the interrupt. Otherwise, the general-purpose registers are restored from
memory, and the PC and PSW registers are popped.
The following processing is made on the hardware.
i. When a write access is made to the current interrupt request level register (CIL), the highest order set bit of the
CIL register is cleared.
ii. If there is an interrupt request flag with a higher interrupt level than the current interrupt request level of the
CIL register among the interrupt request flags which are pending in the interrupt request register (IRQ), an
interrupt request is made to the U16 processor. In this case, if there are multiple interrupt request flags with
higher interrupt levels than the current interrupt request level of the CIL register, the interrupt with the highest
priority is requested to the U16 processor.