Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 26 Analog Comparator
FEUL620Q504 26–8
The timing chart is as follows
Figure 26-3 Timing in the single mode
Time before CMPnD setting becoming valid is depending on operation/sampling clock setting.
CMPn
CK
CMPn
SM1
CMPn
SM0
Operation clock Sampling T
rdy
(time to
judge(interrupt))
T
rdy
+T
end
(time to
comparator off )
0 0 0
Low speed
LSCLK=32.768kHz
No filtering
2φ
61.0 us
3φ
91.6 us
0 0 1 T16KHZ(LTBC
output: 1/2 of
LSCLK)
3φ
183.1 us
4φ
244.2 us
1 0 0
High speed
OSCLK=16MHz
No filtering
3φ
12.0 us
4φ
16.0 us
1 1 0 1/64 of
OSCLK
4φ
16.0 us
5φ
20.0 us
1 1 1 1/128 of
OSCLK
3φ
24.0 us
4φ
32.0 us
System clock
CMPnCLK
CMPnEN
CMPnOUT
CMPnEN
CMPnD
CMPnRF
CMPnINT
with sampling
CMPnEN
CMPnD
CMPnRF
CMPnINT
Trdy
Trdy
Tend
Tend
Sampling clock
without sampling