Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-17
4.3.2.3 Note on Return Operation from STOP/HALT/DEEP-HALT/HALT-H Mode
The operation of returning from the STOP, HALT, DEEP-HALT, or HALT-H mode varies according to the
interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of
the interrupt enable register (IE0 to IE3), and whether the interrupt is a non-maskable interrupt or a maskable
interrupt.
For details of PSW and the IE and IRQ registers, see “nX-U16/100 Core Instruction Manual” and Chapter 5,
“Interrupt”, respectively.
Table 4-1 and Table 4-2 show the return operations from the STOP/HALT/DEEP-HALT/HALT-H mode.
Table 4-1 Return Operation from STOP/HALT/DEEP-HALT/HALT-H Mode (Non-Maskable Interrupt)
ELEVEL MIE IEn.m IRQn.m Return operation from STOP/HALT/DEEP-HALT/HALT-H mode
* * - 0 Not returned from STOP/HALT/DEEP-HALT/HALT-H mode.
3 * - 1
After the mode is returned from the STOP/HALT/DEEP-HALT/
HALT-H mode, the program operation restarts from the instruction
following the instruction that sets the STP/HLT/DEEP-HALT/HALT-H
bit to “1”. The program operation does not go to the interrupt routine.
0,1,2 * - 1
After the mode is returned from the STOP/HALT/DEEP-HALT/
HALT-H mode, program operation restarts from the instruction
following the instruction that sets the STP/HLT/DEEP-HALT/HALT-H
bit to “1”, then goes to the interrupt routine.
Table 4-2 Return Operation from STOP/HALT/DEEP-HALT/HALT-H Mode (Maskable Interrupt)
ELEVEL MIE IEn.m IRQn.m Return operation from STOP/HALT/DEEP-HALT/HALT-H mode
* * * 0
Not returned from STOP/HALT/DEEP-HALT/HALT-H mode.
* * 0 1
* 0 1 1 After the mode is returned from the
STOP/HALT/DEEP-HALT/HALT-H mode, the program operation
restarts from the instruction following the instruction that sets the
STP/HLT/DHLT/HLTH bit to “1”. The program operation does not go
to the interrupt routine.
2,3 1 1 1
0,1 1 1 1
After the mode is returned from the
STOP/HALT/DEEP-HALT/HALT-H mode, program operation restarts
from the instruction following the instruction that sets the
STP/HLT/DHLT/HLTH bit to “1”, then goes to the interrupt routine.
[Note]
•If the ELEVEL bit is 0H, it indicates that the CPU is performing neither non-maskable interrupt processing
nor maskable interrupt processing nor software interrupt processing.
•If the ELEVEL bit is 1H, it indicates that the CPU is performing maskable interrupt processing or software
interrupt processing. (ELEVEL is set during interrupt transition cycle.)
•If the ELEVEL bit is 2H, it indicates that the CPU is performing non-maskable interrupt processing.
(ELEVEL is set during interrupt transition cycle.)
•If the ELEVEL bit is 3H, it indicates that the CPU is performing interrupt processing specific to the emulator.
This setting is not allowed in normal applications.