ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–40
9.3.6 CAPTURE Mode Operation
The CAPTURE mode stores the count value at the time when an event trigger source is generated, to the
FTnEA/FTnEB register. The event trigger source to be captured is common to that used at counter start/stop.
Stored data in FTnEA
Counter value at the time when an event trigger rising edge is generated
Stored data in FTnEB
Counter value at the time when an event trigger falling edge is generated
9.3.6.1 Measurement Example in the CAPTURE Mode
The following example shows the measurement of the period and duty of PWM input from EXI0 using
CAPTURE mode and counter start/stop by trigger events.
Figure 9-5
Measurement example in the CAPTURE mode
Set the FTnMOD register to the capture mode (FTnMD=01b).
Use the FTnINTE register (FTnIETS=1) to enable the trigger counter stop interrupt.
Use the FTnTRG0 register to set the trigger event source to EXI0 (FTnSTSS=0, FTnSTS=00H), enable counter
start (FTnST0=1), and enable counter stop (FTnST1=1).
Use the FTnTRG1 register to set counter start and stop to rising edge (FTnTRM=00b).
Use the FTnCON0 register to enable the trigger operation (FTnTGEN=1).
The counter starts at rising of EXI0. (
)
Then the counter value is stored to the FTnEB register at falling of EXI0. (
)
When the rising of EXI0 is detected again, the counter stops, and an interrupt occurs. (
)
And the counter value is stored to the FTnEA register at rising of EXI0.
At this time, the values of FTnEA and FTnEB correspond to the period and the duty of EXI0 respectively.
EXI0
Counter
FTnEA
Starts counting
Capture
Stop counting
Capture data.
0
Undefined
Value at stop is kept
Capture data.
Undefined
FTnEB
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...