Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 15 I
2
C Bus Interface
FEUL620Q504 15–3
15.2.2 I
2
C Bus n Receive Data Register (I2CnRD : n=0,1)
Address: 0F740H(I2C0RD), 0F750H(I2C1RD)
Access: R
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
I2CnRD I2nR7 I2nR6 I2nR5 I2nR4 I2nR3 I2nR2 I2nR1 I2nR0
R/W R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
I2CnRD is a read-only special function register (SFR) to store the received data.
I2CnRD is updated after completion of each reception.
Description of Bits
•
I2nR7-0 (bits 7 to 0)
The I2nR7-0 bits are used to store the received data. The signal input to the SDA pin is received at
transmission of a slave address and at data transmission/reception in sync with the rising edge of the
signal on the SCL pin. Since data that has been output to the SDA and SCL pins is received not only at
data reception but also at slave address data transmission and data transmission, it is possible to check
whether transmit data has certainly been transmitted.