Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–6
12.2.3 SIOF0 Interrupt Control Register (SF0INTC)
Address: 0F782H
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7 6 5 4 3 2 1 0
SF0INTCL – – – SF0MFIE SF0ORIE SF0FIE SF0RFIE SF0TFIE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
SF0INTCH – –
SF0RFIC1 SF0RFIC0
– –
SF0TFIC1 SF0TFIC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
SF0INTC is a special function register (SFR) used to control the interrupt operation of the SSIOF.
Description of Bits
•
SF0TFIE (bit 0)
SF0TFIE sets whether or not to enable the transmission interrupt of the SSIOF.
SF0TFIE Description
0 Interrupt disabled (initial value)
1 Interrupt enabled
•
SF0RFIE (bit 1)
SF0RFIE sets whether or not to enable the reception interrupt of the SSIOF.
SF0RFIE Description
0 Interrupt disabled (initial value)
1 Interrupt enabled
•
SF0FIE (bit 2)
SF0FIE sets whether or not to enable the transfer end interrupt.
SF0FIE Description
0 Interrupt disabled (initial value)
1 Interrupt enabled
•
SF0ORIE (bit 3)
SF0ORIE sets whether or not to enable the overrun error interrupt.
SF0ORIE Description
0 Interrupt disabled (initial value)
1 Interrupt enabled