Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-12
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UF0PER (bit 2)
UF0PER indicates that a parity error occurred. This is enabled only when parity is enabled. This bit is
cleared when UAF0LSR is read. In FIFO mode, this bit indicates that an error exists for the leading data.
If a parity error occurs in the data that is not the leading data in the FIFO, it is not reflected to this bit.
UF0PER Description
0 No parity error (initial value)
1 Parity error occurred
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UF0FER (bit 3)
UF0FER indicates that a framing error occurred. A framing error indicates that there is no valid stop bit
in the received character. This bit is set to "1" when the stop bit after the last data bit or after the parity
bit is "0" (spacing level). This bit is cleared when UAF0LSR is read. In FIFO mode, the framing error is
related to a specific character in the FIFO. This bit indicates that an error is present when that character
comes to the beginning of the FIFO.
UF0FER Description
0 No framing error (initial value)
1 Framing error occurred
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UF0BI (bit 4)
UF0BI indicates that a break interrupt occurred. This bit is set to "1" when the input data is maintained
in the spacing ("0") state during the transmission of one frame (start bit + data bit + parity bit + stop bit).
This bit will be cleared when the CPU reads UAF0LSR. In FIFO mode, this is related to a specific
character in the FIFO. This bit reflects the break interrupt state when the break character comes to the
beginning of the FIFO. The CPU erases the error if the related character comes to the beginning of the
FIFO before the first reading of UAF0LSR. When a break interrupt occurs, only one zero character will
be loaded into the FIFO.
UF0BI Description
0 No break interrupt (initial value)
1 Break interrupt occurred
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UF0THRE (bit 5)
UF0THRE indicates that preparations have been made for calling a new character to be transmitted by
the UART. This bit is set to "1" when the character is transferred from THR to the shift register for
transmission (TSR). This bit is cleared to "0" by writing to THR. This bit will not be cleared by reading
out the UAF0LSR register. In FIFO mode, this bit is set when the transmit FIFO is empty. This bit is
cleared when one byte is written to the transmit FIFO. If the THRE interrupt is enabled by UF0ETBEI of
UAF0IER, THRE initiates the third-order priority interrupt to UAF0IIR.
UF0THRE Description
0 Transmit data still present in the THR
1 THR ready for transmission (initial value)