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ML620Q503/Q504 User's Manual

Chapter 13 UART

FEUL620Q504

13–19

13.3.5.3

Receive Margin

If there is an error between the sender baud rate and the baud rate generated by the baud rate generator of this
LSI, the error accumulates until the last stop bit loading in one frame, decreasing the receive margin.
Figure 13-9 shows the baud rate errors and receive margin waveforms.

Figure 13-9 Baud Rate Error and Receive Margin

[Note]

In system designing, ensure a sufficient receive margin considering the baud rate difference between sender
and receiver, start bit detection delay, distortion in receive data, and influence of noise.

Sender baud rate is

slow (RXD0)

Sampling timing

U0RSEL=1

U0RSEL=0

Start

Start

Start

Stop

Stop

Stop

Sender baud rate is

fast (RXD0)

Ideal waveform

(RXD0)

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Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503

Page 1: ...chnology and LAPIS Technology succeeded LAPIS Semiconductor s LSI business Therefore all references to LAPIS Semiconductor Co Ltd LAPIS Semiconductor and or LAPIS in this document shall be replaced wi...

Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...

Page 3: ...igned to be radiation tolerant 7 For use of our Products in applications requiring a high degree of reliability as exemplified below please contact and consult with a LAPIS Semiconductor representativ...

Page 4: ...nverter and also on the specifications of the assembler language CCU8 User s Manual Description on the method of operating the compiler CCU8 Programming Guide Description on the method of programming...

Page 5: ...H level 1 level Indicates high voltage signal levels VIH and VOH as specified by the electrical characteristics L level 0 level Indicates low voltage signal levels VIL and VOL as specified by the elec...

Page 6: ...pace 2 2 2 3 Data Memory Space 2 3 2 4 Instruction Length 2 5 2 5 Data Type 2 5 2 6 Description of Registers 2 5 2 6 1 List of Registers 2 5 2 6 2 Data Segment Register DSR 2 5 2 7 Multiplication Divi...

Page 7: ...5 2 1 List of Registers 5 3 5 2 2 Interrupt Enable Register 01 IE01 5 5 5 2 3 Interrupt Enable Register 23 IE23 5 7 5 2 4 Interrupt Enable Register 45 IE45 5 9 5 2 5 Interrupt Enable Register 67 IE67...

Page 8: ...e 6 12 6 3 1 2 Low Speed Crystal Oscillation Mode 6 12 6 3 1 3 Low Speed External Clock Input Mode 6 13 6 3 1 4 Low Speed Built In RC Oscillation Mode Operation 6 14 6 3 1 5 Low Speed Crystal Oscillat...

Page 9: ...2 3 9 9 9 2 5 FTMn DeadTime Register FTnDT n 0 1 2 3 9 10 9 2 6 FTMn Counter Register FTnC n 0 1 2 3 9 11 9 2 7 FTMn Control Register 0 FTnCON0 n 0 1 2 3 9 12 9 2 8 FTMn Control Register 1 FTnCON1 n 0...

Page 10: ...s 11 1 11 2 Description of Registers 11 2 11 2 1 List of Registers 11 2 11 2 2 Serial Port 0 Transmit Receive Buffers SIO0BUF 11 3 11 2 3 Serial Port Control Register SIO0CON 11 4 11 2 4 Serial Port M...

Page 11: ...SSIOF Interrupt Timing 12 29 12 3 16 4 Interrupt processing flow 12 30 12 3 17 Hi Z Operation 12 31 12 3 18 Interval from SF0MST Setting to Transfer Start 12 31 12 3 19 Pin Settings 12 31 Chapter 13...

Page 12: ...s 14 22 14 3 7 Reset By Block Control Register 14 23 Chapter 15 15 I2 C Bus Interface 15 1 15 1 General Description 15 1 15 1 1 Features 15 1 15 1 2 Configuration 15 1 15 1 3 List of Pins 15 1 15 2 De...

Page 13: ...17 2 3 Port 0 Direction Register P0DIR 17 5 17 2 4 Port 0 Control Registers P0CON 17 6 17 2 5 Port 0 Mode Registers P0MOD 17 8 17 3 Description of Operation 17 10 17 3 1 Input Output Port Functions 1...

Page 14: ...20 15 20 3 Description of Operation 20 15 20 3 1 Input Output Port Functions 20 15 20 3 2 Primary Function Other Than Input Output Port 20 15 20 3 3 Secondary to Quartic Functions 20 15 Chapter 21 21...

Page 15: ...Codes 23 10 23 3 5 Scale Codes 23 11 23 3 6 Operations of Buzzer Output 23 12 Chapter 24 24 RC Oscillation Type A DConverter RC ADC 24 1 24 1 General Description 24 1 24 1 1 Features 24 1 24 1 2 Confi...

Page 16: ...6 2 2 Comparator n Control Register CMPnCON n 0 1 26 3 26 2 3 Comparator n mode Registers CMPnMOD n 0 1 26 4 26 3 Function description 26 6 26 3 1 Comparator function 26 6 26 3 2 Supervisor mode 26 6...

Page 17: ...8 5 28 3 Description of Operation 28 7 28 3 1 Supervisor mode 28 8 Chapter 29 29 LLD circuit 29 1 29 1 General Description 29 1 29 1 1 Features 29 1 29 2 Description of resister 29 1 29 3 Description...

Page 18: ...Chapter 1 Overview...

Page 19: ...ic operations jump conditional jump call return stack manipulations arithmetic shift and so on Build in On Chip debug function Minimum instruction execution time 30 5 s 32 768 kHz system clock 62 5ns...

Page 20: ...K 32 768 kHz Synchronous serial port SSIOF SSIO without FIFOs SSIO 1 channel with 4 byte transmits and receives FIFOs SSIOF 1 channel Master slave are selectable LSB first MSB first are selectable 8 b...

Page 21: ...e the operation without low speed clock Crystal oscillation 32 768 kHz External clock input 30kHz to 36kHz Built in RC oscillation 32 768kHz High speed clock Crystal Ceramic oscillation 16 MHz Externa...

Page 22: ...t our responsible sales person for the pad layout information 48 pin plastic TQFP Tray ML620Q503 xxxTBZWAAL ML620Q504 xxxTBZWAAL Tape and Reel ML620Q503 xxxTBZWABL ML620Q504 xxxTBZWABL Guaranteed oper...

Page 23: ...ler Instruction Register TBC INT 3 INT 3 INT 2 INT 1 WDT INT 8 Timer 8 INT 4 Function Timer x 4 GPIO PXT0 to PXT1 P10 to P11 P20 to P23 INT 8 P30 to P37 P40 to P47 Data bus TMOUTA F TEST0 RESET_N OSC...

Page 24: ...TXD0 5 SINF0 TXDF0 2 SCK0 TMOUT 6 SCKF0 TMOUT 3 MD0 P33 only TMOUT 7 SSF0 TMOUT Figure 1 2 Pin Layout of ML620Q503 Q504 TQFP Package 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 2...

Page 25: ...stor capaci tor sensor connection pin SCK0 I O SSIO clock input output TMOUT0 O FTM output 22 P03 EXI03 AIN11 I O Hi Z output Input Output port External interrupt SA ADC input RS0 O RC ADC reference r...

Page 26: ...put output TMOUT8 O FTM output 28 P43 EXI43 TMCKI 1 I O Hi Z output Input Output port External interrupt Timer clock input MD0 O Melody Buzze r output TMOUT9 O FTM output 29 P44 EXI44 I O Hi Z output...

Page 27: ...4th Function Pin name I O Reset State Function pin name I O function pin name I O function pin name I O functio n 40 P57 EXI57 TMCKI 7 I O Hi Z output Input Output port External interrupt Timer clock...

Page 28: ...lock 16 MHz max Capacitors CDH and CGH are connected across this pin and Vss P10 1st OSC1 O P11 1st CLKIN I External clock input for High speed clock P11 1st LSCLKO O Low speed clock output pin P46 P5...

Page 29: ...in P02 P32 P42 P52 3rd SIN0 I Synchronous serial SSIO data input pin P01 P31 P41 P51 3rd SOUT0 O Synchronous serial SSIO data output pin P00 P30 P40 P50 3rd SCKF0 I O Synchronous serial with FIFO SSIO...

Page 30: ...erted input pin P31 1st CMP1P I Comparator1 Non inverted input pin P32 1st CMP1M I Comparator1 Inverted input pin P33 1st For testing TEST0 I O Input output pin for testing A pull down resistor is int...

Page 31: ...1_N open VREF Connect to VDD P00 to P05 open PXT0 to PXT1 open P10 to P11 open P20 to P23 open P30 to P37 open P40 to P47 open P50 to P57 open Note For unused input ports or unused input output ports...

Page 32: ...Chapter 2 CPU and Memory Space...

Page 33: ...urn stack manipulations arithmetic shift and so on Built in On chip debug function Minimum instruction execution time 30 5 s 32 768kHz system clock 62 5ns 16MHz system clock Multiplication division co...

Page 34: ...of the program memory space CSR PC Code segment 0 0 0000H Vector table or Program code 0 00FFH 0 0100H Program code 0 7BFFH 0 7C00H Test data area Rewritable 0 7DFFH 0 7E00H Test data area Not rewrit...

Page 35: ...itable as data area For writing to this area see Chapter 27 Flash Memory Control Note that the flash data area cannot be operated as program memory The data memory stores 8 bit data and is specified b...

Page 36: ...7 0800H 0 D7FFH Unused area 0 D800H RAM area 0 EFFFH 0 F000H SFR area 0 FFFFH 7 FFFFH 8bit 8bit DSR DADR Data segment 8 Data segment F 8 0000H Code segment 0 Reference area F 0000H F 07FFH Data segmen...

Page 37: ...1 0 DSR DSR3 DSR2 DSR1 DSR0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 DSR is a special function register SFR used to retain a data segment For details of DSR see nX U16 100 Cor...

Page 38: ...ion the result is fixed to 7FFF_FFFFH for a positive number and 8000_0000H for a negative number when it is out of the expressible range 2 7 2 List of Registers These are byte type registers for carry...

Page 39: ...8 CR3 BREG15 BREG14 BREG13 BREG12 BREG11 BREG10 BREG9 BREG8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 CR4 CREG7 CREG6 CREG5 CREG4 CREG3 CREG2 CREG1 CREG0 R W R...

Page 40: ...saturating and multiply accumulate saturating CLMOD2 CLMOD1 CLMOD0 Description 0 0 0 Multiplication initial value 16bit 16bit 0 0 1 Division 32bit 16bit 0 1 0 Multiply accumulate non saturating 16bit...

Page 41: ...e operation The value is held in the next operation To reset it to 0 0 needs to be written OV bit 4 This becomes 1 if the operation result exceeds the range expressible by two s complement This is set...

Page 42: ...0 1 Multiply accumulate saturating 0 1 Changes according to the result No change 2 7 2 4 Coprocessor ID Register CR15 Access R Access size 8 bits Initial value 81H 7 6 5 4 3 2 1 0 CR15 COPID7 COPID6 C...

Page 43: ...et the multiplicand MOV R1 12H MOV CR4 R0 Transfer the multiplier 7 0 MOV R0 90H Set the operation mode MOV CR8 R0 Set the signed operation mode MOV CR5 R1 Transfer the multiplier 15 8 MOV CR6 R2 Tran...

Page 44: ...Chapter 3 Reset Function...

Page 45: ...pin has an internal pull up resistor 125 ms 1 500ms 2 sec or 8 sec can be selected as the watchdog timer WDT overflow period when LSCLK 32 768 kHz Built in reset status register RSTAT indicating the...

Page 46: ...4 User s Manual Chapter 3 Reset Function FEUL620Q504 3 2 3 2 Description of Registers 3 2 1 List of Registers Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F00C Reset status registe...

Page 47: ...r on reset not occurred 1 Power on reset occurred WDTR bit 2 The WDTR is a flag that indicates that the watchdog timer reset is generated This bit is set to 1 when the reset by overflow of the watchdo...

Page 48: ...onality Reset status register RSTAT VLSR bit becomes 1 at system reset occurred by VLS Reset by Low Level Detector LLD System reset occur when Power supply Voltage falls than threshold 1 8V Typ LLD re...

Page 49: ...SFR that has a fixed initial value is initialized either Therefore initialize such an SFR by software The cause that shifted to System reset mode and the internal status of LSI are as below Initializ...

Page 50: ...Chapter 4 Power Management...

Page 51: ...igh speed clock is automatically stopped when the CPU stops operating DEEP HALT mode where the CPU stops operating and only LTBC and timer can operate at lower power consumption STOP mode where both l...

Page 52: ...ol Word R W Size Initial value H 0F008 Stop code acceptor STPACP W 8 0F009 Standby control register SBYCON W 8 00 0F068 Block control register 01 BLKCON0 BLKCON01 R W 8 16 00 0F069 BLKCON1 R W 8 00 0F...

Page 53: ...s set to 1 in this state the mode is changed to the STOP mode When the STOP mode is set the STOP code acceptor is disabled When another instruction is executed between the instruction that writes 5nH...

Page 54: ...1 the mode is changed to the DEEP HALT mode Writing 0 to the DHLT bit does not change the mode to the DEEP HALT mode HLTH bit 3 The HLTH bit is used for setting the HALT H mode When the HLTH bit is s...

Page 55: ...each block operation Description of Bits DTM7 0 bits 7 to 0 The DTM7 0 bits are used to control the 8 bit timer operation DTM0 Description 0 Enable operating the timer 0 initial value 1 Disable operat...

Page 56: ...he FTM 0 DFTM1 Description 0 Enable operating the FTM1 initial value 1 Disable operating the FTM 1 DFTM2 Description 0 Enable operating the FTM 2 initial value 1 Disable operating the FTM 2 DFTM3 Desc...

Page 57: ...al port operation DSIO0 Description 0 Enable operating the synchronous serial port 0 initial value 1 Disable operating the synchronous serial port 0 DSIOF0 bit 1 The DSIOF0 bit is used to control the...

Page 58: ...dy driver 0 DCMP0 bit 14 The DCMP0 bit is used to control the operation of the analog comparator 0 DCMP0 Description 0 Enable operating the analog comparator 0 initial value 1 Disable operating the an...

Page 59: ...e A D converter operation DSAD Description 0 Enable operating the SA type A D converter initial value 1 Disable operating the SA type A D converter DRAD bit 1 The DRAD bit is used to control the RC os...

Page 60: ...tion the function of the applicable block is reset all registers are initialized and the clock supply to that block stops While the flag is set to 1 the writing to the registers of the block becomes i...

Page 61: ...m run mode HALT mode Interrupt request Program run mode SBYCON HLT HSCLK Figure 4 2 1 Operation Waveforms in HALT Mode FCON1 SYSCLK 1 FCON1 ENOSC 1 SYSCLK LSCLK Program run mode HALT mode Interrupt re...

Page 62: ...a system clock is a high speed clock it returns to program operational mode simultaneously In the case of high speed crystal oscillation mode oscillation is started after high speed oscillation start...

Page 63: ...rrupt request the interrupt enable flag is 1 is issued in this state HLTH is set to 0 the high speed clock restarts the operation and the mode returns to the program run mode About restart of a high s...

Page 64: ...k When the stop code acceptor is in the enabled state and the STP bit of SBYCON is set to 1 the STOP mode is entered stopping low speed oscillation and high speed oscillation When an external pin inte...

Page 65: ...of high speed crystal ceramic oscillation mode oscillation is started after high speed oscillation start time TXTH from LSCLK supply And OSCLK changes from RC oscillation into crystal oscillation by...

Page 66: ...upt processing Therefore place two NOP instructions next to the instruction that set the STP bit to 1 Low speed RC oscillation Oscillation waveform SYSCLK SBYCON STP bit LSCLK crystal RC OSCLK program...

Page 67: ...ollowing the instruction that sets the STP HLT DEEP HALT HALT H bit to 1 then goes to the interrupt routine Table 4 2 Return Operation from STOP HALT DEEP HALT HALT H Mode Maskable Interrupt ELEVEL MI...

Page 68: ...ctions in STOP HALT DEEP HALT HALT H Mode Function HALT HALT H 2 DEEP HALT 2 STOP CPU RAM Retain Retain Retain Retain Watchdog timer External Interrupt Acceptable Acceptable Acceptable Acceptable LTBC...

Page 69: ...nsure to reset the applicable flag of this block control register to 0 enable operation BLKCON0 register Controls enables disables the circuit operation of timers 0 to 7 BLKCON1 register Controls enab...

Page 70: ...Chapter 5 Interrupts...

Page 71: ...ial Port SSIO Chapter 12 Synchronous Serial Port with FIFO SSIOF Chapter 13 UART Chapter 14 UART with FIFO UARTF Chapter 15 I2C Bus Interface Chapter 23 Melody Driver Chapter 24 RC Oscillation type A...

Page 72: ...terrupt control register ILEN Interrupt level control enable register EXI SEL External interrupt mode register ILC Interrupt level control register Figure 5 1 Configuration of Circuit Data bus int to...

Page 73: ...ble register ILENL ILEN R W 8 16 00 0F021 ILENH R W 8 00 0F022 Current interrupt request level register CILL CIL R W 8 16 00 0F023 CILH R W 8 00 0F024 Interrupt level control register 1 ILC1L ILC1 R W...

Page 74: ...Initial value H 0F04A External interrupt 23 selection register EXI2SEL EXI23SEL R W 8 16 00 0F04B EXI3SEL R W 8 00 0F04C External interrupt 45 selection register EXI4SEL EXI45SEL R W 8 16 00 0F04D EX...

Page 75: ...ch interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE01 is not reset Description of Bits EEXI0 bit 8 EEXI0 is the enable...

Page 76: ...bled EEXI5 bit 13 EEXI5 is the enable flag for the external interrupt 5 EXI5INT EEXI5 Description 0 Disabled initial value 1 Enabled EEXI6 bit 14 EEXI6 is the enable flag for the external interrupt 6...

Page 77: ...uest When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE23 is not reset Description of Bits ESIO0 bit 0 ESIO0 is the enable flag for the syn...

Page 78: ...it 6 EUAF0 is the enable flag for the UART0 transmission interrupt with FIFO UAF0INT EUAF0 Description 0 Disabled initial value 1 Enabled ELOSC bit 13 ELOSC is the enable flag for the low speed oscill...

Page 79: ...st When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE45 is not reset Description of Bits ESAD bit 0 ESAD is the enable flag for the success...

Page 80: ...abled ETM3 bit 11 ETM3 is the enable flag for the 8 bit timer 3 interrupt TM3INT ETM3 Description 0 Disabled initial value 1 Enabled ETM4 bit 12 ETM4 is the enable flag for the 8 bit timer 4 interrupt...

Page 81: ...upt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE67 is not reset Description of Bits EFTM0 bit 0 EFTM0 is the enable flag for...

Page 82: ...t LTB0INT ELTBC0 Description 0 Disabled initial value 1 Enabled ELTBC1 bit 9 ELTBC1 is the enable flag for the time base counter 1 interrupt LTB1INT ELTBC1 Description 0 Disabled initial value 1 Enabl...

Page 83: ...e MIE value when an interrupt is generated Each IRQ1 request flag is set to 1 regardless of the IE1 and MIE values when an interrupt is generated In this case an interrupt is requested to the CPU when...

Page 84: ...rupt 3 EXI3INT QEXI3 Description 0 No request initial value 1 Request QEXI4 bit 12 QEXI4 is the request flag for the external interrupt 4 EXI4INT QEXI4 Description 0 No request initial value 1 Request...

Page 85: ...nterrupts FEUL620Q504 5 15 Note When an interrupt is generated by the write instruction to the interrupt request register IRQ1 or to the interrupt enable register IE1 the interrupt shift cycle starts...

Page 86: ...In this case an interrupt is requested to the CPU when the related flag of the interrupt enable register IE23 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ23 requ...

Page 87: ...UA1INT QUA1 Description 0 No request initial value 1 Request QUAF0 bit 6 QUAF0 is the request flag for the UART0 interrupt with FIFO UAF0INT QUAF0 Description 0 No request initial value 1 Request QLO...

Page 88: ...terrupts FEUL620Q504 5 18 Note When an interrupt is generated by the write instruction to the interrupt request register IRQ23 or to the interrupt enable register IE23 the interrupt shift cycle starts...

Page 89: ...n this case an interrupt is requested to the CPU when the related flag of the interrupt enable register IE45 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ45 reque...

Page 90: ...terrupt TM1INT QTM1 Description 0 No request initial value 1 Request QTM2 bit 10 QTM2 is the request flag for the 8 bit timer 2 interrupt TM2INT QTM2 Description 0 No request initial value 1 Request Q...

Page 91: ...t initial value 1 Request QTM7 bit 15 QTM7 is the request flag for the 8 bit timer 5 interrupt TM7INT QTM7 Description 0 No request initial value 1 Request Note When an interrupt is generated by the w...

Page 92: ...generated In this case an interrupt is requested to the CPU when the related flag of the interrupt enable register IE67 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the...

Page 93: ...tial value 1 Request QLTBC1 bit 9 QLTBC1 is the request flag for the time base counter 1 interrupt LTB1INT QLTBC1 Description 0 No request initial value 1 Request QLTBC2 bit 10 QLTBC2 is the request f...

Page 94: ...r ILEN is a special function register SFR used to control enable disable for the interrupt level control Description of Bits ILE bit 0 The ILE bit controls enable disable for the interrupt level contr...

Page 95: ...eptance of interrupt requests is prohibited below the interrupt level indicated by the highest order bit position set to 1 It indicates that the processing is being done for an interrupt with the leve...

Page 96: ...rrupt level 3 is in processing CILM3 Description 0 Interrupt level 4 is not in processing initial value 1 Interrupt level 4 is in processing CILN bit 7 Indicates whether CPU is processing a non maskab...

Page 97: ...rrupt source enabled by IE1 Write access to this register is possible only when the interrupt level control is enabled by the ILEN register Level 1 to 4 can be set for each interrupt source The regist...

Page 98: ...errupt 5 EXI5INT L1EXI5 L0EXI5 Description 0 0 Level 1 initial value 0 1 Level 2 1 0 Level 3 1 1 Level 4 L1 0EXI6 bits 13 to 12 L1 0EXI6 set the level of the external interrupt 6 EXI6INT L1EXI6 L0EXI6...

Page 99: ...E2 Write access to this register is possible only when the interrupt level control is enabled by the ILEN register Level 1 to 4 can be set for each interrupt source The register which has the higher l...

Page 100: ...1 Level 4 L1 0UA1 bits 11 to 10 L1 0UA1 set the level of the UART0 transmission interrupt UA1INT L1UA1 L0UA1 Description 0 0 Level 1 initial value 0 1 Level 2 1 0 Level 3 1 1 Level 4 L1 0UAF0 bits 13...

Page 101: ...Write access to this register is possible only when the interrupt level control is enabled by the ILEN register Level 1 to 4 can be set for each interrupt source The register which has the higher lev...

Page 102: ...upts FEUL620Q504 5 32 Note A write instruction to the interrupt level control register 3 ILC3 should be executed after disabling the interrupt Except this way the write instruction to the interrupt le...

Page 103: ...ter is possible only when the interrupt level control is enabled by the ILEN register Level 1 to 4 can be set for each interrupt source The register which has the higher level is given the higher prio...

Page 104: ...1 interrupt CMP1INT L1CMP1 L0CMP1 Description 0 0 Level 1 initial value 0 1 Level 2 1 0 Level 3 1 1 Level 4 Note A write instruction to the interrupt level control register 4 ILC4 should be executed a...

Page 105: ...source enabled by IE5 Write access to this register is possible only when the interrupt level control is enabled by the ILEN register Level 1 to 4 can be set for each interrupt source The register wh...

Page 106: ...interrupt TM5INT L1TM5 L0TM5 Description 0 0 Level 1 initial value 0 1 Level 2 1 0 Level 3 1 1 Level 4 L1 0TM6 bits 13 to 12 L1 0TM6 set the level of the 8 bit timer 6 interrupt TM6INT L1TM6 L0TM6 De...

Page 107: ...access to this register is possible only when the interrupt level control is enabled by the ILEN register Level 1 to 4 can be set for each interrupt source The register which has the higher level is g...

Page 108: ...3 interrupt FTM3INT L1FTM3 L0FTM3 Description 0 0 Level 1 initial value 0 1 Level 2 1 0 Level 3 1 1 Level 4 Note A write instruction to the interrupt level control register 6 ILC6 should be executed a...

Page 109: ...gister is possible only when the interrupt level control is enabled by the ILEN register Level 1 to 4 can be set for each interrupt source The register which has the higher level is given the higher p...

Page 110: ...upts FEUL620Q504 5 40 Note A write instruction to the interrupt level control register 7 ILC7 should be executed after disabling the interrupt Except this way the write instruction to the interrupt le...

Page 111: ...ICON01 is a special function register SFR used to select the interrupt edge of external interrupt Description of Bits EXI7 0E0 bits 7 to 0 EXI7 0E1 bits 15 to 8 The EXI7 0E0 and EXI7 0E1 bits are used...

Page 112: ...dge of external interrupt Description of Bits EXI7 0SM bits 7 to 0 The EXI7 0SM bits are used to select detection of signal edge for an external interrupt with or without sampling The sampling clock i...

Page 113: ...f the port used as EXI0 The EXI0S7 4 registers are used to select the group of the port used as EXI0 Example When EXI0S7 4 5 and EXI0S3 0 1 Port 51 is used as EXI0 EXI0S7 4 EXI0S3 0 0 1 2 3 4 5 6 7 0...

Page 114: ...L620Q504 5 44 Note A write instruction to the External Interrupt Selection Register EXI01SEL should be executed after disabling the interrupt to be changed And the request bit which correspond to the...

Page 115: ...f the port used as EXI2 The EXI2S7 4 registers are used to select the group of the port used as EXI2 Example When EXI2S7 4 5 and EXI2S3 0 1 Port 51 is used as EXI2 EXI2S7 4 EXI2S3 0 0 1 2 3 4 5 6 7 0...

Page 116: ...L620Q504 5 46 Note A write instruction to the External Interrupt Selection Register EXI23SEL should be executed after disabling the interrupt to be changed And the request bit which correspond to the...

Page 117: ...f the port used as EXI4 The EXI4S7 4 registers are used to select the group of the port used as EXI4 Example When EXI4S7 4 5 and EXI4S3 0 1 Port 51 is used as EXI4 EXI4S7 4 EXI4S3 0 0 1 2 3 4 5 6 7 0...

Page 118: ...L620Q504 5 48 Note A write instruction to the External Interrupt Selection Register EXI45SEL should be executed after disabling the interrupt to be changed And the request bit which correspond to the...

Page 119: ...t of the port used as EXI6 The EXI6S7 4 registers are used to select the group of the port used as EXI6 Example When EXI6S7 4 5 and EXI6S3 0 1 Port 51 is used as EXI6 EXI6S7 4 EXI6S3 0 0 1 2 3 4 5 6 7...

Page 120: ...L620Q504 5 50 Note A write instruction to the External Interrupt Selection Register EXI67SEL should be executed after disabling the interrupt to be changed And the request bit which correspond to the...

Page 121: ...014H 8 EXI3 interrupt EXI3INT 0016H 9 EXI4 interrupt EXI4INT 0018H 10 EXI5 interrupt EXI5INT 001AH 11 EXI6 interrupt EXI6INT 001CH 12 EXI7 interrupt EXI7INT 001EH 13 Synchronous serial port 0 interrup...

Page 122: ...ase counter 0 interrupt LTB0INT 0070H 54 Time base counter 1 interrupt LTB1INT 0072H 55 Time base counter 2 interrupt LTB2INT 0074H Note When multiple interrupts are generated concurrently they are pr...

Page 123: ...ssing of program shifts to the interrupt destination 1 Transfer PC to ELR2 2 Transfer CSR to ECSR2 3 Transfer PSW to EPSW2 4 Set the ELEVEL field to 2 5 Load the interrupt start address into PC 5 3 4...

Page 124: ...d of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW A 1 2 When multiple interrupts are enabled Proce...

Page 125: ...interrupts are enabled Processing immediately after the start of interrupt routine execution Specify PUSH LR ELR EPSW to save the interrupt return address the subroutine return address and the EPSW st...

Page 126: ...xecution Specify POP PC PSW instead of the RTI instruction to return the saved data of the interrupt return address to PC and the saved data of EPSW to PSW B 2 2 When a subroutine is called by the pro...

Page 127: ...xample of description B 2 2 Intrpt_B 2 2 Start PUSH ELR EPSW LR Save ELR EPSW LR at the beginning Sub_1 BL Sub_1 Call subroutine Sub_1 RT Return PC from LR POP PC PSW LR Return PC from the stack End o...

Page 128: ...to the current interrupt request level register CIL to clear the highest current interrupt request level iii If the interrupt is in the highest level the general purpose registers are restored from m...

Page 129: ...tructions due to the specification of U16 processor Execute desired processing Interrupt processing end Restore return PC to PC and pre interrupt PSW to PSW from stack Write access to the current inte...

Page 130: ...L620Q504 5 60 Execute desired processing Interrupt processing end Restore general purpose registers from memory RTI instruction Write access to current interrupt level register CIL Non maskable interr...

Page 131: ...ion at the beginning of the interrupt routine When the interrupt conditions are satisfied in this interval an interrupt is generated immediately following the execution of the instruction at the begin...

Page 132: ...is filtered by noise filter not sampling without relation for control of EXICON23 Figure 5 2 shows the interrupt generation timing in rising edge interrupt mode in falling edge interrupt mode and in...

Page 133: ...er s Manual Chapter 5 Interrupts FEUL620Q504 5 63 d When Rising Edge Interrupt Mode with Sampling is Selected Figure 5 2 External Interrupt Generation Timing SYSCLK EXIn EXInINT Interrupt request QEXI...

Page 134: ...Chapter 6 Clock Generation Circuit...

Page 135: ...ation mode External clock input mode Interrupt generation at low speed clock mode shift High speed clock generation circuit Crystal ceramic oscillation mode Built in RC oscillation mode External clock...

Page 136: ...ircuit FEUL620Q504 6 2 Note After power on or system reset the operation starts by the clock supplied from the built in high speed clock generation circuit At initialization by software set the FCON0...

Page 137: ...cting a crystal for low speed clock XT1 LSCLKI I O Pin for connecting a crystal for low speed clock Used for low speed external clock input OSC0 I Pin for connecting a crystal ceramic oscillator for h...

Page 138: ...ource oscillation clock OSCLK System clock SYSCLK LTBC FTM RC ADC UART SA ADC U16 LSCLK High speed clock HSCLK Register access Register access Register access Register access Register access Register...

Page 139: ...sters 6 2 1 List of Registers Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F002 Frequency control register 01 FCON0 FCON01 R W 8 16 73 0F003 FCON1 R W 8 03 0F004 Frequency control...

Page 140: ...value 0 0 0 0 0 0 1 1 FCON01 is a special function register SFR used to control the high speed clock generation circuit and to select system clock Description of Bits SYSC2 0 bits 2 to 0 The SYSC2 0...

Page 141: ...TC2 0 bits 7 to 5 The OUTC2 OUTC1 and OUTC0 bits select the frequency of the high speed output clock OUTCLK output when the secondary function of the port is used 1 1OSCLK 1 2OSCLK 1 4OSCLK 1 8OSCLK 1...

Page 142: ...crystal oscillation when the low speed built in RC oscillation mode is selected LOSST bit 14 LOSST is the flag used to indicate the oscillation state of the low speed crystal oscillator circuit LOSST...

Page 143: ...e previous value is held 0 1 Low speed Crystal oscillation mode 1 0 Low speed Built in RC oscillation mode initial value 1 1 External low speed clock input mode Note When switching the clock mode from...

Page 144: ...gh speed clock input mode Two different eliminaton width are selectable When noise filter is on at 16MHz high speed clock operation select High speed clock noise filter1 HFLTSEL1 HFLTSEL0 Description...

Page 145: ...ating in the high speed crystal ceramic oscillation mode or the external clock input mode 1 Operating with the high speed built in RC oscillator circuit initial value For the high speed crystal cerami...

Page 146: ...the oscillation frequency by using a trimmer capacitor connect external capacitors CGL and CDL as required Figure 6 4 Circuit Configuration of the Crystal Oscillation Mode Note Install the crystal os...

Page 147: ...gure 6 5 Circuit Configuration in the External Clock Input Mode Note Since the PXT1 pin has a built in diode to VDD and VSS avoid applying voltages higher than the VDD and lower than the VSS If the PX...

Page 148: ...ernal interrupt The built in RC oscillation clock is counted to 29 as the low speed clock then the built in RC oscillation clock LSCLK is supplied to the peripheral circuits For STOP mode see Chapter...

Page 149: ...oscillation clock In this time the low speed oscillation clock switch interrupt LOSCINT is generated Refer to Chapter 4 Power Management for the operation at each power down mode Figure 6 7 Low Speed...

Page 150: ...the low speed oscillation clock switch interrupt LOSCINT is generated Refer to Chapter 4 Power Management for the operation at each power down mode Figure 6 8 Low Speed Clock Generation Circuit Operat...

Page 151: ...oscillation In crystal ceramic oscillation mode a crystal or a ceramic oscillator is externally connected to the P10 OSC0 and P11 OSC1 pins If the high speed oscillation clock pulse count reaches 4096...

Page 152: ...onfiguration in the External Clock Input Mode Note Since the P11 OSC1 pin has a built in diode to VDD and VSS avoid applying voltages higher than the VDD and lower than the VSS If the P11 OSC1 pin is...

Page 153: ...oscillation mode or external clock input mode high speed built in oscillation starts after the low speed clock is counted to 26 The high speed clock generation circuit stops oscillation when it shift...

Page 154: ...Low speed RC oscillation 29 counts Built in RC oscillation Built in RC oscillation High speed RC oscillation 512 counts ENOSC bit External interrupt occurred OSCLK STOP mode Built in RC oscillation Hi...

Page 155: ...gh speed built in oscillation starts after the low speed clock is counted to 26 The high speed clock generation circuit stops oscillation when it shifts to the STOP mode by software When the mode swit...

Page 156: ...4096 counts Built in RC oscillation RC oscillation 512 counts Crystal ceramic Built in RC oscillation Crystal ceramic OSCLK switch TXTH oscillation start time ENOSC bit External interrupt occurred OSC...

Page 157: ...is counted to 512 then the built in RC oscillation clock is supplied as OSCLK And OSCLK changes from RC oscillation into external clock by the automatic operation in case of 128 counts by the externa...

Page 158: ...oscillation High speed built in RC oscillation High speed External clock HOSCS bit RC oscillation 512 counts Low speed oscillation Low speed oscillation Low speed RC oscillation 29 counts OSCM 11 Exte...

Page 159: ...ate until LSCLK starts to be supplied to the peripheral circuits Figure 6 16 Flow Chart of System Clock Switching Processing LSCLK HSCLK System clock switching ENOSC 1 Wait of the oscillation stabiliz...

Page 160: ...n clock change interrupt occurs only when switching the mode from low speed built in RC oscillation mode to low speed crystal oscillation mode or external low speed clock input mode The interrupt does...

Page 161: ...Chapter 7 Time Base Counter...

Page 162: ...adjustment registers LTBADJH and LTBADJL 3clocks between 128Hz and 1Hz can be used as interrupt signal 7 1 2 Configuration Figure 7 1 show the configuration of a low speed time base counter respectiv...

Page 163: ...Name Symbol Byte Symbol Word R W Size Initial value H 0F060 Low speed time base counter register LTBR R W 8 00 0F062 Low speed time base counter frequency adjustment register LTBADJL LTBADJ R W 8 16...

Page 164: ...Z T32HZ T64HZ T128HZ R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 LTBR is a special function register SFR to read the T128HZ T1HZ outputs of the low speed time base counter When w...

Page 165: ...ment range Approx 488ppm to 488ppm Adjustment accuracy Approx 0 48ppm Frequency adjustment Adjustment range Approx 488ppm to 488ppm Adjustment accuracy Approx 0 48ppm is possible for outputs of T8KHZ...

Page 166: ...g time Adjustment value 15 0ppm 2097152 decimal 15 0 10 6 2097152 31 45728 decimal 01Fh hexadecimal Example 2 When adjusting 25 5ppm losing time Adjustment value 25 5ppm 2097152 decimal 25 5 10 6 2097...

Page 167: ...R W R W Initial value 0 0 0 0 0 1 1 0 LTBINT is a special function register SFR which specify low speed time base clock which is used as an interrupt signal Description of Bits LTI0S2 0 bit 2 to 0 Th...

Page 168: ...is performed and the T128HZ to T1HZ outputs are set to 0 At this time Interrupt occurs when clock is assigned to LTBC interrupt changing from 1 to 0 Therefore when LTBR is reset After prohibits each...

Page 169: ...FEUL620Q504 7 8 Figure 7 4 shows interrupt generation timing of the time base counter output by writing to LTBR Figure 7 4 Interrupt Timing by Writing to LTBR LTBR Write T1HZ T2HZ T4HZ T8HZ T16HZ T32...

Page 170: ...Chapter 8 Timers...

Page 171: ...clock selectable clock is different every channel Timer clock can be divided by 1 2 4 8 16 32 and 64 by divider function 8 1 2 Configuration Figure 8 1 shows the configuration of the timers a In 8 bi...

Page 172: ...ernal pin P53 6 LSCLK OSCLK low speed crystal oscillation 1 7 16 bit mode case channel Selectable clock 0 1 LSCLK OSCLK 2 3 LSCLK OSCLK external pin P42 4 5 LSCLK OSCLK external pin P52 6 7 LSCLK OSCL...

Page 173: ...R W 8 16 00 0F311 TM1C R W 8 00 0F312 Timer 23 counter register TM2C TM23C R W 8 16 00 0F313 TM3C R W 8 00 0F314 Timer 45 counter register TM4C TM45C R W 8 16 00 0F315 TM5C R W 8 00 0F316 Timer 67 cou...

Page 174: ...nD7 TnD6 TnD5 TnD4 TnD3 TnD2 TnD1 TnD0 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 TMmD TmD7 TmD6 TmD5 TmD4 TmD3 TmD2 TmD1 TmD0 R W R W R W R W R W R W R W...

Page 175: ...l function register SFR that functions as an 8 bit binary counter When write random data to TMnC TMmC TMnC is cleared to 00H In 16 bit timer mode the combination becomes TM0C and TM1C TM2C and TM3C TM...

Page 176: ...FR register to control a timer Timer control register TMnCON is a special function register SFR which control timer Timer control register setting need to be done while target timer is stop TMSTAT0 re...

Page 177: ...or selecting a 16 bit timer mode TM0CON TM2CON TM4CON and TM6CON has the TnmM16 bit When the TnmM16 is set to 1 two timers are connected and function as a 16bit timer When the TnmM16 bit is set to 0 t...

Page 178: ...s the control bit of Timer n count start In initial state after power on the counter is stopped Timer n Count up is started by writing TnRUN bit to 1 Timer n and n 1 count up is started at 16bit timer...

Page 179: ...ount stop control bit Counter is stop at initial state after power on 1 setting while count stop is invalid Timer n Count up is stopped by setting TnSTP bit to 1 Timer n and n 1 count up is stopped at...

Page 180: ...SFR to control timer 0 to timer 7 Description of Bits TnSTAT bits n n 0 to 7 TnSTAT bit indicate timer n status counting stopping TnSTAT Description 0 Stopping initial value 1 counting 8 bit timer mo...

Page 181: ...restart an incremental count from the previous values To initialize TMnC to 00H perform write operation in TMnC The timer interrupt period TTMI is expressed by the following equation TTMI TMnD 1 n 0 7...

Page 182: ...egister TnM16 bit At 16bit timer mode channel n n 0 2 4 6 is lower bit channel m m 1 3 5 7 is higher bit The following shows a corresponding list of timer channels and related registers channel Contro...

Page 183: ...Chapter 9 Function Timer FTM...

Page 184: ...ck The timer output signal can be switched between the positive and negative logics Duty interrupt and coincident interrupt with the setting value as well as the cyclic interrupt generated Equipped wi...

Page 185: ...n trigger register 0 1 FTnINTE S C FTMn interrupt enable status clear register Figure 9 1 a Configuration of Circuit FTnC 16 Data FTMnINT HSCLK R Period matched TMCKI Write FTnC FTnCK Event A matched...

Page 186: ...3 List of Pins Pin Name I O Function TMCLKI0 7 I External clock input TMOUT0 9 TMOUTA F O Timer output selectable from FTM 0 to 3 Data bus FTM0P FTMOSnN 16 FTOSLn0 1 P02 TMOUT0 P03 TMOUT1 P22 TMOUT2 P...

Page 187: ...3 FT0TRG1H R W 8 00 0F418 FTM0 interrupt enable register FT0INTEL FT0INTE R W 8 16 00 0F419 FT0INTEH R W 8 00 0F41A FTM0 interrupt status register FT0INTSL FT0INTS R 8 16 00 0F41B FT0INTSH R 8 00 0F41...

Page 188: ...2 FTM2 trigger register 1 FT2TRG1L FT2TRG1 R W 8 16 00 0F453 FT2TRG1H R W 8 00 0F458 FTM2 interrupt enable register FT2INTEL FT2INTE R W 8 16 00 0F459 FT2INTEH R W 8 00 0F45A FTM2 interrupt status reg...

Page 189: ...0F482 FTM output 23 select register FTO2SL FTO23SL R W 8 16 00 0F483 FTO3SL R W 8 00 0F484 FTM output 45 select register FTO4SL FTO45SL R W 8 16 00 0F485 FTO5SL R W 8 00 0F486 FTM output 67 select reg...

Page 190: ...15 FTnP14 FTnP13 FTnP12 FTnP11 FTnP10 FTnP9 FTnP8 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 FTnP is a special function register SFR used to set the cycle clock count of one cyc...

Page 191: ...ecial function register SFR used to set the event timing of FTMn or indicate the captured data Set this register after setting the operation mode using FTnMD In the CAPTURE mode this is a read only re...

Page 192: ...0 0 FTnEB is a special function register SFR used to set the event timing of FTMn or indicate the captured data Set this register after setting the operation mode using FTnMD In the CAPTURE mode this...

Page 193: ...15 14 13 12 11 10 9 8 FTnDT15 FTnDT14 FTnDT13 FTnDT12 FTnDT11 FTnDT10 FTnDT9 FTnDT8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 FTnDT is a special function register SFR used to s...

Page 194: ...6 FTnC5 FTnC4 FTnC3 FTnC2 FTnC1 FTnC0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 FTnC15 FTnC14 FTnC13 FTnC12 FTnC11 FTnC10 FTnC9 FTnC8 R W R W R W R W R W...

Page 195: ...ing of FTMn by the software FTnMD FTnRUN Description TIMER CAPTURE PWM1 2 0 Stop counting initial value 1 Start counting during counting FTnTGEN bit 1 Allow stopping starting counting by a trigger eve...

Page 196: ...tnEB and FTnDT at the same time When the transfer completes this bit is cleared automatically FTnMD FTnUD Description TIMER CAPTURE PWM1 2 0 Update completed initial value 1 Requesting update Note To...

Page 197: ...t of FTMn When FTnC is read it is cleared FTnMD FTnFLGC Description TIMER PWM1 2 CAPTURE 0 Start enable state by event trigger initial value 1 Start disable state by event trigger FTnSTAT bit 7 Indica...

Page 198: ...nMD0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 FTnMODH FTnSTPO R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 FTnMOD is a special funct...

Page 199: ...arts from 0 1 Single mode Once captured into EA or EB the next capture is not performed before read When the counter goes round it stops Note When using the One shot mode Single mode set to 1 FTnIEP o...

Page 200: ...0 15 14 13 12 11 10 9 8 FTnCLKH FTnXCK2 FTnXCK1 FTnXCK0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 FTnCLK is a special function register SFR used to set the function of FTMn De...

Page 201: ...er FTM FEUL620Q504 9 18 FTnXCK2 0 bits 10 to 8 Selects the source when selecting EXTCLK as a timer clock source of FTMn FTnMD FTnXCK Description TIMER CAPTURE PWM1 2 0 TMCKI0 initial value 1 TMCKI1 2...

Page 202: ...R W Initial value 0 0 0 0 0 0 0 0 FTnTRG0 is a special function register SFR used to set the function of FTMn Description of Bits FTnST0 bit 0 Selects whether a trigger event starts the counter FTnMD...

Page 203: ...TM0 for the FTM0 setting FTnMD FTnSTS Description S 3 2 1 0 TIMER CAPTURE PWM1 2 0 0 0 0 0 EXI0TGO initial value 0 0 0 0 1 EXI1TGO 0 0 0 1 0 EXI2TGO 0 0 0 1 1 EXI3TGO 0 0 1 0 0 EXI4TGO 0 0 1 0 1 EXI5T...

Page 204: ...sed to set the function of FTMn Description of Bits FTnTRM1 0 bits 1 to 0 Selects the edge of the trigger event for FTMn It is enabled only when EXI0 7 is selected as the event trigger source Otherwis...

Page 205: ...upt of FTMn Setting a bit of FTnINTE to 1 makes the interrupt enabled and notifies the interrupt controller Description of Bits FTnIEP bit 0 Sets the period interrupt enable of FTMn FTnMD FTnIEP Descr...

Page 206: ...8 Outputs a period interrupt request of FTMn as the trigger for another peripheral FTnMD FTnIOP Description TIMER CAPTURE PWM1 2 0 Period interrupt trigger disabled initial value 1 Period interrupt tr...

Page 207: ...e the interrupt status of FTMn FTnINTS is a read only register Writing to it has no effect Description of Bits FTnISP bit 0 Indicates the period interrupt state of FTMn FTnMD FTnISP Description TIMER...

Page 208: ...stop interrupt state of FTMn FTnMD FTnISTS Description TIMER CAPTURE PWM1 2 0 Trigger counter stop interrupt has not occurred initial value 1 Trigger counter stop interrupt has occurred This bit is cl...

Page 209: ...0 0 0 0 0 0 0 0 FTnINTC is a special function register SFR used to clear the interrupt status of FTMn When writing 1 to this bit the target interrupt status is cleared When reading it 0000H is always...

Page 210: ...W Initial value 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 FTOmSL FTOmSN FTOmS2 FTOmS1 FTOmS0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 FTOnmSL is a special function register SFR u...

Page 211: ...M output that is assigned TMOUTx X 0 F output signal FTOnS2 FTOmS2 FTOnS1 FTOmS1 FTOnS0 FTOmS0 Description 0 0 0 FTM0P Initial value 0 0 1 FTM0N 0 1 0 FTM1P 0 1 1 FTM1N 1 0 0 FTM2P 1 0 1 FTM2N 1 1 0 F...

Page 212: ...dead time can be set using the FTMnDeadTimer register FTMnDT 9 3 1 Common Sequence FTM starts control by FTnCON0 after setting 1 6 described below as needed Then it processes interrupts and updates c...

Page 213: ...op are synchronized by FTnCK FTnSTAT is set to H after FTnCK1 cycle at start and the counter starts operating after two cycles At stop the counter is stopped in FTnCK1 cycle and FTnSTAT is set to L Th...

Page 214: ...FTnMOD is 1 FTnRUN bit is automatically set to 0 when the counter stops due to overflow If the counter is operating FTnSTAT bit of the FTMn control register 1 FTnCON1 is 1 the counter stops when FTnRU...

Page 215: ...the counter value is 0000H FTMnP starts with L and FTMnN starts with H when FTnRUN bit of the FTMn control register 0 FTnCON0 is set to 1 In the one shot mode it stops after outputting H pulse of one...

Page 216: ...620Q503 Q504 User s Manual Chapter 9 Function Timer FTM FEUL620Q504 9 33 FTnP Counter FTnSTAT FTMnP FTMnN FTMnP FTMnN b TIMER mode output waveform auto reload mode FTnDT Without dead time With dead ti...

Page 217: ...H FTnCK Hz Tdeadtime FTnDT 1 FTnDT 0000H to FFFEH FTnCK Hz Figure 9 2 waveform in TIMER mode FTnP BUF FTnEA BUF FTnEB BUF FTMnP FTnFLGA FTnFLGB Counter Auto reload mode FTMnN FTnSTAT FTMnP One shot mo...

Page 218: ...eload mode the initial values of FTMnP and FTMnN are L and they change to H at start Each of them changes to L at the duty value It changes to H in the next period This is repeated until they stop In...

Page 219: ...nual Chapter 9 Function Timer FTM FEUL620Q504 9 36 Figure 9 3 waveform in PWM1 mode FTnP Counter FTnSTAT FTMnP FTMnN FTMnP FTMnN b PWM1 mode output waveform auto reload mode FTnDT Without dead time Wi...

Page 220: ...L and FTMnP changes to H at start FTMnP changes to L and FTMnN changes to H at the duty value FTMnP changes to H and FTMnN changes to L in the next period This is repeated until they stop In the one...

Page 221: ...504 User s Manual Chapter 9 Function Timer FTM FEUL620Q504 9 38 FTnP Counter FTnSTAT FTMnP FTMnN FTMnP FTMnN b PWM2 mode output waveform auto reload mode FTnDT FTnEA FTnEA FTnDT With dead time Without...

Page 222: ...nEA 1 FTnA FTnB 0000H to FFFEH FTnCK Hz Tdeadtime1 FTnDT 1 FTnDT 0000H to FFFEH FTnCK Hz FTnP BUF FTnEA BUF FTnEB BUF FTMnP FTnFLGA FTnFLGB Counter Auto reload mode FTMnN FTnSTAT FTMnP One shot mode F...

Page 223: ...RE mode Set the FTnMOD register to the capture mode FTnMD 01b Use the FTnINTE register FTnIETS 1 to enable the trigger counter stop interrupt Use the FTnTRG0 register to set the trigger event source t...

Page 224: ...FTnEA is not updated at falling of EXI0 Figure 9 6 a FTnEA FTnEB register read before next trigger FTnOST 0 1 Figure 9 6 b Next trigger occurred without register read FTnOST 0 Figure 9 6 c Next trigg...

Page 225: ...unter and sets output FTMnP FTMnN to L CMP0TGO CMP1TGO interrupt EXI0TGO or EXI4TGO can be selected as the trigger source The analog filter output of the interrupt controller is connected to the EXI0...

Page 226: ...3 Controlling FTnCON0 Set FTnTGEN to 1 to enter the waiting state for event triggers Then set FTnRUN to 1 to start the counter by the software Set FTnRUN to 0 during the counter operation to stop the...

Page 227: ...it is cleared to 0 When the STAT bit is 1 setting the RUN to 1 is not accepted Confirm that the STAT has changed to 0 after clearing the interrupt status before running the next RUN Figure 9 9 Operati...

Page 228: ...e counter is restarted in this state the FTMnP FTMnN outputs keep L during that period and they change according to the counter value from the next period When FTnSTPO is 1 FTMnP FTMnN keep the state...

Page 229: ...the FTnCON1 register to request the update The values in the buffers for the period event A B and dead time are updated at the beginning of the next period and the FTnUD bit is set to 0 Here is an ex...

Page 230: ...ear Period coincident interrupt ALL FTnISP Write 1 to FTnICP Event A coincident interrupt TIMER PWM1 PWM2 FTnISA Write 1 to FTnICA Capture A interrupt CAPTURE FTnISA Write 1 to FTnICA or read FTnEA Ev...

Page 231: ...Chapter 10 Watchdog Timer...

Page 232: ...Reset Function 10 1 1 Features Free running stop setting in DEEP HALT mode is available Count low speed clock 128 period One of four types of overflow periods 125ms 500ms 2s and 8s LSCLK 32 768kHz sel...

Page 233: ...Timer FEUL620Q504 10 2 10 2 Description of Registers 10 2 1 List of Registers Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F00E Watchdog timer control register WDTCON R W 8 00 0F0...

Page 234: ...bit7 bit1 WDP is reset to 0 at system reset and at overflow For WDT counter clear write 5AH when WDP state is 0 and write 0A5H when WDP state is 1 If WDT state is different from above WDT counter can...

Page 235: ...access always Description of Bits WDT1 0 bits 1 to 0 These bits are used to select an overflow period of the watchdog timer The WDT1 and WDT0 bits set a overflow period TWOV of the WDT counter It is...

Page 236: ...eriod TWOV of the WDT counter one of 125ms 500ms 2s and 8s can be selected by the watchdog mode register WDTMOD Clear the WDT counter within the clear period of the WDT counter shown in Table 10 1 Tab...

Page 237: ...r are initialized While it is initialized the writing to WDTCON becomes invalid and internal pointer doesn t turn over If the WDT counter is not cleared even by the software processing performed follo...

Page 238: ...Watchdog timer cannot be stopped Even when the watchdog timer function is not used as failsafe measures it is necessary to clear WDT counter The example program which clears WDT counter at WDT interru...

Page 239: ...Chapter 11 Synchronous Serial Port SSIO...

Page 240: ...phase and polarity of clock 11 1 2 Configuration Figure 11 1 shows the configuration of the synchronous serial port SIO0BUF Serial port transmit receive buffer SIO0CON Serial port control register SI...

Page 241: ...1 List of Registers Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F700 Serial port 0 transmit receive buffer SIO0BUFL SIO0BUF R W 8 16 00 0F701 SIO0BUFH R W 8 00 0F702 Serial port 0...

Page 242: ...R W Initial value 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SIO0BUFH S0B15 S0B14 S0B13 S0B12 S0B11 S0B10 S0B9 S0B8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 SIO0BUF are special fu...

Page 243: ...0 SIO0CON is a special function register SFR to control the synchronous serial port 0 Description of Bits S0EN bit 0 The S0EN bit is used to specify start of synchronous serial communication Writing a...

Page 244: ...ial function register SFR to set mode of the synchronous serial port 0 Description of Bits S0DIR bit 0 The S0DIR is used to select LSB first or MSB first S0DIR Description 0 LSB first initial value 1...

Page 245: ...xternal clock 0 SCK0 1 1 1 reserved S0CKT bit 12 The S0CKT bit is used to select a transfer clock output phase S0CKT Description 0 Clock type 0 Clock is output with a H level being the default Initial...

Page 246: ...ter mode and when an external clock SCK0 is selected the LSI is set to a slave mode The serial port mode register SIO0MOD enables selection of MSB first LSB first The transmit data output pin SOUT0 an...

Page 247: ...f Synchronous Serial Port for Clock Type 1 8 bit Length LSB first Positive Logic Figure 11 5 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 8 bit Length LSB first Negative Lo...

Page 248: ...e serial port mode register SIO0MOD enables selection of MSB first or LSB first The receive data input pin SIN0 and transfer clock input output pin SCK0 must be set to the tertiary function Figures 11...

Page 249: ...9 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 1 8 bit Length MSB first Negative Logic Note When the SOUT0 pin is set to the tertiary function output in receive mode a H level...

Page 250: ...lock input output pin SCK0 must be set to the tertiary function Figure 11 10 shows the transmit receive operation waveforms of the synchronous serial port 16 bit length LSB first clock types 0 and pos...

Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...

Page 252: ...word can be selected The number of received bytes words that cause interrupts can be set to 1 to 4 The number of untransmitted bytes words that cause interrupts can be set to 0 to 3 Either LSB first o...

Page 253: ...Rshifter Rshifter Rfifo_H Rfifo_L SCKF0 Control section SSF0 SYSCLK Register interface Interrupt signal P20 P34 P44 P54 P21 P35 P45 P55 P22 P36 P46 P56 P23 P37 P47 P57 LSCLK HSCLK Figure 12 1 Configur...

Page 254: ...C R W 8 16 00 0F783 SF0INTCH R W 8 00 0F784 SIOF0 transfer interval control register SF0TRAC R W 16 0002 0F786 SIOF0 baud rate register SF0BRR R W 16 5002 0F788 SIOF0 status register SF0SRRL SF0SRR R...

Page 255: ...function register SFR used to control the operation of the SSIOF Description of Bits SF0SPE bit 0 SF0SPE sets whether or not to enable the transfer of the SSIOF SF0SPE Description 0 Disable SSIOF tra...

Page 256: ...clock polarity SF0CPOL Description 0 Serial clock default is 0 0 during transmission reception initial value 1 Serial clock default is 1 1 during transmission reception SF0FICL bit 8 SF0FICL sets the...

Page 257: ...R used to control the interrupt operation of the SSIOF Description of Bits SF0TFIE bit 0 SF0TFIE sets whether or not to enable the transmission interrupt of the SSIOF SF0TFIE Description 0 Interrupt d...

Page 258: ...ords initial value 0 1 An interrupt occurs when the number of remaining byte to transmit becomes 1 byte 1 word 1 0 An interrupt occurs when the number of remaining byte to transmit becomes 2 bytes 2 w...

Page 259: ...ue 0002H 7 6 5 4 3 2 1 0 SF0DTL7 SF0DTL6 SF0DTL5 SF0DTL4 SF0DTL3 SF0DTL2 SF0DTL1 SF0DTL0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 1 0 15 14 13 12 11 10 9 8 SF0DTL8 R W R W R W R W...

Page 260: ...transfer Operation is not guaranteed if it is changed during transfer Description of Bits SF0BR9 0 bits 9 to 0 Sets the baud rate fSCK setting enabled in Master mode fSCK fHLSCLK 2 SF0BR9 0 fHLSCLK H...

Page 261: ...ous Serial Port with FIFO FEUL620Q504 12 10 SF0LAG1 0 bits 15 to 14 SF0LAG1 0 set the SCKF0 SSF0 H delay interval setting enabled only in Master mode SF0LAG1 SF0LAG0 Description 0 0 0 5 X SCK 0 1 0 5...

Page 262: ...escription of Bits SF0TFI bit 0 SF0TFI indicates a transmission interrupt A transmission interrupt occurs if the remaining data in the transmit FIFO matches the byte count selected with SF0TFIC SF0TFI...

Page 263: ...transfer end SF0SPIF Description 0 No end of transfer initial value 1 End of transfer SF0WOF bit 8 SF0WOF indicates a write overflow SF0WOF Description 0 Normal initial value 1 A write overflow occur...

Page 264: ...04 User s Manual Chapter 12 Synchronous Serial Port with FIFO FEUL620Q504 12 13 SF0RFE bit 12 SF0RFE indicates the receive FIFO Empty SF0RFE Description 0 Not Empty 1 Empty No interrupt is generated i...

Page 265: ...ng interrupt The interrupt request is cleared by writing 1 For the interrupt request check on the SF0RFI bit of SF0SRR SF0FC bit 2 SF0FC clears the interrupt request of the transfer end interrupt The...

Page 266: ...e 1 to SF0IRQ bit while there is any unprocessed interrupt source and processing all the interrupt sources before exiting the interrupt vector will cause re entry to the interrupt vector with no inter...

Page 267: ...0 0 0 SF0FSR is a special function register SFR used to indicate the count transmitted and received by FIFO Description of Bits SF0TFD2 0 bits 2 to 0 SF0TFD2 0 indicate the untransmitted byte word co...

Page 268: ...R W R W Initial value 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SF0DWRH SF0WD15 SF0WD14 SF0WD13 SF0WD12 SF0WD11 SF0WD10 SF0WD9 SF0WD8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 SF0...

Page 269: ...R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SF0DRRH SF0RD15 SF0RD14 SF0RD13 SF0RD12 SF0RD11 SF0RD10 SF0RD9 SF0RD8 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SF0DRR i...

Page 270: ...transmit data and the sampling timing of received data The master and slave which communicate with each other must have the same setting values for SF0CPOL and SF0CPHA 12 3 3 Data Transfer Timing Whe...

Page 271: ...g edge of SCKF0 in SF0CPOL is 1 CPHA 1 SSN MOSI MOZ 0 BIT 0 BIT 7 BIT 7 BIT 0 SCK Cycle 1 2 3 4 5 6 7 8 MISO SOZ 0 SCK CPOL 0 SCK CPOL 1 MOZ SOZ SSZ SIZE LSBF LEAD LAG 0 Figure 12 3 Clock Waveform Whe...

Page 272: ...other must have the same value for SF0SIZ CPHA 0 SCK CPOL 0 SSN MOSI BIT 0 BIT 7 BIT7 MISO BIT0 SCK Cycle 1 2 3 4 5 6 7 8 BIT8 BIT15 BIT8 BIT15 9 10 11 12 13 14 15 16 SCK CPOL 1 Figure 12 4 SSIOF Bus...

Page 273: ...The minimum transfer interval can be controlled in SCKF0 clocks by setting SF0TRAC s SF0DTL If there is any transfer data in FIFO the time set by this setting SSF0 changes to H during byte word transf...

Page 274: ...nchronous Serial Port with FIFO FEUL620Q504 12 23 1 2 3 4 5 6 7 8 2 3 4 5 6 7 LEAD 1 2 3 4 5 6 7 8 2 3 4 5 6 7 SCKF0 SCKF0 Cycle SOUTF0 SINF0 SSF0 Continuous data Continuous clock LSB MSB LSB MSB Figu...

Page 275: ...SF0DWR successively However if further writing is performed when the transmit FIFO is in Full status SF0TFF 1 a write overflow occurs SF0WOF 1 No interrupt is generated The SF0SPIF bit is set each tim...

Page 276: ...y flag changes to 0 RFE 0 The SF0SPIF bit is set each time the transfer of 1 byte is completed SF0SPIF 1 If the number of data received in the receive FIFO is equal to or more than matches following t...

Page 277: ...receive FIFO is in Full status SF0RFF 1 an overrun error occurs SF0ORF 1 If an overrun error occurs the SF0ORF bit of SF0SRR is set and an overrun error interrupt is generated The newly received data...

Page 278: ...ansmitted data is not written in the slave s FIFO a 0xFF 0xFFFF for word is sent including the state after a reset SSN MOSI write from APB bus TFE TFD 1 0 SP E data S1 2 1 0 spcr data M1 MISO FFH data...

Page 279: ...lly sets the SF0SPE bit of SF0CTRL to 0 disabled to make the SSIOF unable to transfer 3 Set SF0MDF of SF0SRR and also generates an interrupt if the SF0MDFE bit of SF0CTRL is 1 interrupt permitted The...

Page 280: ...t to generate a reception interrupt End of transfer If the transmit FIFO becomes empty and the transfer of the last byte is finished SF0FI of SF0SRR is set to generate a transfer end interrupt 12 3 16...

Page 281: ...interrupt control flow Clear processing of SF0RFI Write 1 in SF0SRC SF0RFC Interrupt factor check SF0SRR SF0RFI SSIOF Interrupt occurrence Check processing unprocessed interrupt source Write 1 in SF0...

Page 282: ...by data write 12 3 19 Pin Settings To enable the SSIOF function the applicable bit of each related port register needs to be set See Chapter 19 Port 2 Chapter 20 Port 3 Chapter 21 Port 4 and Chapter 2...

Page 283: ...Chapter 13 UART...

Page 284: ...parity or no parity selectable 1 stop bit or 2 stop bits selectable Provided with parity error flag overrun error flag framing error flag and transmit buffer status flag Positive logic or negative lo...

Page 285: ...nitial value H 0F710 UART0 receive buffer UA0BUF R W 8 00 0F711 UART0 control register UA0CON R W 8 00 0F712 UART0 mode register UA0MOD0 UA0MOD R W 8 16 00 0F713 UA0MOD1 R W 8 00 0F714 UART0 baud rate...

Page 286: ...er reception terminates Any write to UA0BUF is disabled When the 5 to 7 bit data length is selected unnecessary bits become 0 13 2 3 UART0 Transmit Buffer UA1BUF Address 0F718H Access R W Access size...

Page 287: ...0 0 0 UA0CON is a special function register SFR used to start stop communication of the UART Description of Bits U0EN bit 0 The U0EN bit is used to specify the UART communication operation start When...

Page 288: ...U1EN R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 UA1CON is a special function register SFR which indicate UART transmission status Description of Bits U1EN bit 0 The bit indicat...

Page 289: ...he transfer mode of the UART Description of Bits U0CK1 0 bits 2 to 1 The U0CK1 0 bits are used to select the clock to be input to the baud rate generator of the UART0 U0CK1 U0CK0 Description 0 0 LSCLK...

Page 290: ...t length in the communication of the UART U0STP Description 0 1 stop bit initial value 1 2 stop bit U0NEG bit 13 The U0NEG bit is used to select positive logic or negative logic in the communication o...

Page 291: ...l value 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 UA0BRTH U0BR11 U0BR10 U0BR9 U0BR8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 1 1 1 1 UA0BRT is special function registers SFRs to set the c...

Page 292: ...ption 0 No framing error initial value 1 With framing error U0OER bit 1 The U0OER bit is used to indicate occurrence of an overrun error of the UART If the received data in the transmit receive buffer...

Page 293: ...operations When any data is written to UA1STAT all the flags are initialized to 0 Description of Bits U1FUL bit 3 U1FUL indicates the UART transmit buffer state When the transmitted data is written i...

Page 294: ...sitive logic or negative logic can be selected All these options are set with the UART0 mode register UA0MOD1 Figure 13 2 and Figure 13 3 show the positive logic input output format and negative logic...

Page 295: ...T is expressed by the following equation UA0BRT Clock frequency Hz 1 Baud rate bps Table 13 1 lists the count values for typical baud rates Table 13 1 Count Values for Typical Baud Rates Baud rate Bau...

Page 296: ...B transmission Data length 7 bits Data length 6 bits U0B7 is 0 at completion of reception Data length 5 bits MSB reception UnB6 UnB3 UnB5 UnB2 UnB1 UnB4 UnB0 LSB transmission LSB reception MSB recepti...

Page 297: ...is output a UART0 interrupt is requested In the UART0 interrupt routine the next data to be transmitted is written to the transmit buffer UA1BUF When the next data to be transmitted is written to the...

Page 298: ...UA1BUF write instruction U0EN set instruction 1st data 2nd data BRT BRT Start 0 1 2 7 Parity Stop Start 0 1 2 7 Parity Stop Transmit receive buffer write enable period Transmit receive buffer write en...

Page 299: ...gister and 5 to 8 bit received data is transferred to the receive buffer UA0BUF concurrently with the falling edge of the internal transfer clock of The LSI requests a UART reception interrupt on the...

Page 300: ...rt 0 1 6 7 Parity Stop Parity Stop Start 0 1 2 7 1st data 2nd data Parity error Overrun error Detection of start bit Parity error overrun error framing error detected UART0 interrupt request Stop rece...

Page 301: ...rate then loaded to the shift register The loading sampling timing of this shift register can be adjusted for one clock of the baud rate generator clock using the U0RSS bit of the UART0 mode register...

Page 302: ...the receive margin Figure 13 9 shows the baud rate errors and receive margin waveforms Figure 13 9 Baud Rate Error and Receive Margin Note In system designing ensure a sufficient receive margin consid...

Page 303: ...Chapter 14 UART with FIFO UARTF...

Page 304: ...ny time The information that can be read out consists of the type and status of the transfer operation under execution and the statuses of errors such as parity overrun framing errors and break interr...

Page 305: ...he configuration of the UARTF BUF RBR LCR BUF DLR LSR BUF THR IER IIR FCR Baud rate generation RSR Receive control TSR Transmiss ion control MUX for reading Interrupt control Bus control reset RXDF0 P...

Page 306: ...8 16 xx 0F7C1 UAF0BUFH R W 8 00 0F7C2 UARTF0 interrupt enable register UAF0IERL UAF0IER R W 8 16 00 0F7C3 UAF0IERH R W 8 00 0F7C4 UARTF0 interrupt status register UAF0IIRL UAF0IIR R 8 16 01 0F7C5 UAF...

Page 307: ...rallel conversion operation the register has the double buffer configuration so that read operations can be made RBR can be read by program when UF0DLAB of UAF0MOD is 0 When UAF0BUF is read RBR can be...

Page 308: ...ived data read request interrupt including character timeout interrupt in the FIFO mode UF0ERBFI Description 0 Disable the received data read request interrupt Includes the character timeout interrupt...

Page 309: ...R R R R R R R Initial value 0 0 0 0 0 0 0 0 UAF0IIR is a special function register SFR used to indicate the UART state in interrupt transmit receive operations UAF0IIR stores information indicating t...

Page 310: ...able FIFO enabled Reached the Trigger level Read RBR or when FIFO drops below trigger level 110 2 Character timeout At least one character is present in the receive FIFO and no other character was pla...

Page 311: ...tion register SFR used to set the mode of the UART Description of Bits UF0LG1 0 bits 1 to 0 UF0LG1 0 specify the character length of UARTF0 UF0LG1 UF0LG0 Description 0 0 5 bit length initial value 0 1...

Page 312: ...THR are accessible When this is 1 DLR is accessible UF0DLAB Description 0 RBR and THR of UAF0BUF are accessible initial value 1 DLR of UAF0BUF is accessible UF0FEN bit 8 UF0FEN selects whether FIFO is...

Page 313: ...Chapter 14 UART with FIFO UARTF FEUL620Q504 14 10 UF0FTL1 0 bits 15 to 14 UF0FTL1 0 select the trigger level for the receive FIFO interrupt UF0FTL1 UF0FTL0 Description 0 0 1 byte initial value 0 1 2 b...

Page 314: ...in the IIR if any of the states is detected This interrupt is enabled by setting UF0ELSI of UARTF0IER to 1 Description of Bits UF0DR bit 0 UF0DR is set to 1 when the input character has been received...

Page 315: ...input data is maintained in the spacing 0 state during the transmission of one frame start bit data bit parity bit stop bit This bit will be cleared when the CPU reads UAF0LSR In FIFO mode this is re...

Page 316: ...shift register are empty UF0TEMT Description 0 Transmitted data remains in either THR or TSR 1 Both THR and TSR are empty initial value UF0RFE bit 7 UF0RFE is always 0 when FIFO is disabled In the FI...

Page 317: ...W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 UAF0CAJ is a special function register SFR used to adjust the base clock for the baud rate clock of UARTF0 Description of Bits UF0CAJ4 0 bits 4 to 0 Adj...

Page 318: ...special function register SFR used to issue an interrupt request again if there is an unprocessed interrupt source Description of Bits UF0IRQ bit 0 When there is any unprocessed interrupt source the...

Page 319: ...bit the most significant bit will not be sent If parity is enabled by UF0PT2 0 of UAF0MOD then the parity bit is sent This is followed by the stop bit which indicates the end of transmitting one frame...

Page 320: ...F0 subsequent data is obtained and transferred to the receive shift register The data in the receive shift register is transferred to RBR through the receive FIFO When the data reaches RBR UF0DR of UA...

Page 321: ...3 Buad rate Clocks tRINT MAX 1 Baud rate Clock Figure 14 5 First Byte of Receive FIFO Set RBR RXDF0 Start Data bit 5 8 Parity Stop Sample CLK FIFO below Trigger Level UAF0INT Received Data Available t...

Page 322: ...the DLR 8 setting in an ideal state of 16MHz SYSCLK Make sure that the margin of error between the actual and set baud rates is within a few percent Note Divisor DLR 15 0 cannot be set to 1 Set a val...

Page 323: ...e first stop bit is calculated An amount of time required to transfer at least 4 characters has elapsed since the receive FIFO was last read For example if 1 start bit 8 character bits 1 parity bit 2...

Page 324: ...to UF0DR When UF0PER is cleared to 0 an interrupt will not be generated even if an error is detected while receiving a character The error state will not be indicated on the UAF0IIR value Therefore t...

Page 325: ...a in the FIFO it is not reflected to UF0PER of UAF0LSR c Framing error A framing error indicates that there is no valid stop bit in the received character This error will occur when the stop bit after...

Page 326: ...reset a sequence is the following 1 Set DUAF0 bit to 1 If it is in the UARTF is transmission state the TXD output will become indetermination 2 Set DUAF0 bit to 0 again The block reset is completed i...

Page 327: ...Chapter 15 I2 C Bus Interface...

Page 328: ...clude standard mode 100kbps and fast mode 400kbps 7 bit address format 10 bit address can be supported 15 1 2 Configuration Figure 15 1 shows the configuration of the I2 C bus interface I2CnRD I 2 C b...

Page 329: ...6 00 0F747 I2C0CON1 R W 8 00 0F748 I 2 C bus 0 mode register I2C0MODL I2C0MOD R W 8 16 00 0F749 I2C0MODH R W 8 02 0F74A I 2 C bus 0 status register I2C0STAL I2C0STA R 8 16 00 0F74B I2C0STAH R 8 00 0F7...

Page 330: ...to store the received data I2CnRD is updated after completion of each reception Description of Bits I2nR7 0 bits 7 to 0 The I2nR7 0 bits are used to store the received data The signal input to the SD...

Page 331: ...I2nA0 I2nRW R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 I2CnSA is a special function register SFR to set the address and the transmit receive mode of the slave device Description...

Page 332: ...I2C1TD Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 I2CnTD0 I2nT7 I2nT6 I2nT5 I2nT4 I2nT3 I2nT2 I2nT1 I2nT0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 I2CnTD...

Page 333: ...on operation of the I2 C bus interface When the I2nST bit is set to 1 communication starts When 1 is overwritten to the I2nST bit in a control register setting wait state after transmission reception...

Page 334: ...art condition and communication restarts from the slave address I2nRS can be set to 1 only while communication is active I2nST 1 When the I2nRS bit is read 0 is always read I2nRS Description 0 No rest...

Page 335: ...hen I2nEN is 1 the I2nST bit can be set and the I2Cn bus becomes available When I2nEN is set to 0 all the SFRs related to I2 C bus n I2CnMODH register is excluded are initialized I2nEN Description 0 S...

Page 336: ...r less Proper operation cannot be guaranteed if the frequency division value exceeds 4MHz Table 15 1 shows the relationship between the setting values of OSCLK I2nCD1 and I2nCD0 and the communication...

Page 337: ...e acknowledgment signal received Acknowledgment signals are received each time the slave address is received and data transmission or reception is completed The I2nACR bit is set to 0 when the I2nEN b...

Page 338: ...irection of the I2 C bus n slave address register I2CnSA are transmitted in MSB first and finally the acknowledgment signal is received in the I2nACR bit of the I2 C bus n status register I2CnSTAT At...

Page 339: ...confirmed and at data reception the contents of I2CnRD are read in the CPU and the next operation mode is selected When 1 is written to the I2nST bit in the control register setting wait state the LSI...

Page 340: ...D 7 A D 6 D 7 D 0 A D 6 D 7 D 0 A P I2CnCON 02H Value of I2CnnTD Value of I2CnTD Value of I2CnSA Value of I2CnSA Value of I2CnTD Value of I2CnTD Value of I2CnTD Register setting SDA I2CMINT I2nST I2Cn...

Page 341: ...TAT is set to 1 and the SDA pin output is disabled until termination of the subsequent byte data communication Figure 15 6 shows the operation timing and control method when transmission fails Figure...

Page 342: ...U DAT tSU STO tBUF Standard mode 100kbps No reduction 40 18 22 4 18 22 18 18 22 10 reduction 44 20 24 4 20 24 20 20 24 20 reduction 48 22 26 4 22 26 22 22 26 30 reduction 52 24 28 4 24 28 24 24 28 Fas...

Page 343: ...Chapter 21 Port 4 and Chapter 22 Port 5 for details about the port registers For SCLn and SDAn the ports can be selected from several possibilities Be sure to select one of the following combinations...

Page 344: ...Chapter 16 Port XT...

Page 345: ...ircuit 16 1 1 Features Can be used as a high impedance input Can be used as an external interrupt pin EXII0 to EXII1 a low speed crystal oscillation pin or an external clock input pin 16 1 2 Configura...

Page 346: ...XT FEUL620Q504 16 2 16 2 Description of Registers 16 2 1 List of Registers Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F208 Port XT data register PXTD R 8 Depends on pin state 0F2...

Page 347: ...R R R R R R R Initial value 0 0 0 0 0 0 x x PXTD is a read only special function register SFR used to read the input level of the port XT pin Description of Bits PXT1 0D bits 1 to 0 The PXT1 0D bits...

Page 348: ...function of the port XT pin Description of Bits PXT01DIR bit 0 The PXTDIR bit is used to enable the input port function of the port XT pin PXT01DIR Description 0 Input port function of the PXT0 and P...

Page 349: ...t mode is selected In the low speed crystal oscillation mode both the PXT0 and PXT1 pins are used as the pins for crystal oscillation In the external clock input mode the PXT1 pin is used as the input...

Page 350: ...Chapter 17 Port 0...

Page 351: ...pull up resistor in input mode for each bit External interrupt inputs EXI00 EXI01 EXI02 EXI03 EXI04 EXI05 the SA ADC input pins AIN8 AIN9 AIN10 AIN11 The RC ADC channel 0 oscillation pins IN0 CS0 RS0...

Page 352: ...connection pin for RC ADC CS0 SSIO data input SIN0 UART data output TXD0 P02 EXI02 AIN10 RCT0 SCK0 TMOUT0 I O Input output port External Interrupt SA ADC AIN10 Resistor capacitor sensor connection pi...

Page 353: ...egisters Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F210 Port 0 data register P0D R W 8 00 0F211 Port 0 direction register P0DIR R W 8 00 0F212 Port 0 control register P0CON0 P0C...

Page 354: ...the port 0 direction register P0DIR described later Description of Bits P05 P00D bits 5 to 0 The P05 00D bits are used to set the output value of the Port 0 pin in output mode and to read the pin lev...

Page 355: ...he input output mode of Port 0 Description of Bits P05 00DIR bits 5 to 0 The P05 00DIR pins are used to set the input output direction of the Port 0 pin P00DIR Description 0 P00 pin Output initial val...

Page 356: ...rain output N channel open drain output or CMOS output in output mode and to select high impedance input input with a pull down resistor or input with a pull up resistor in input mode Setting of P00 p...

Page 357: ...1 0 P03 pin N channel open drain output P03 pin Input with a pull up resistor 1 1 P03 pin CMOS output P03 pin High impedance input Setting of P04 pin When output mode is selected P04DIR bit 0 When in...

Page 358: ...pin P00MD1 P00MD0 Description 0 0 General purpose input output mode External Interrupt initial value 0 1 RC oscillation waveform input pin for RC ADC IN0 1 0 SSIO data output SOUT0 1 1 UART data inpu...

Page 359: ...r connection pin for measurement for RC ADC RT0 1 0 Prohibited 1 1 Prohibited P05MD1 0 bit 13 5 The P05MD1 0 bits are used to select the primary or secondary function of the P05 pin P05MD1 P05MD0 Desc...

Page 360: ...Port 0 data register P0D In input mode the input level of each pin of Port 0 can be read from the Port 0 data register P0D 17 3 2 Primary Function except for Input Output Port Port 0 is assigned to t...

Page 361: ...Chapter 18 Port 1...

Page 362: ...input input with a pull down resistor or input with a pull up resistor for each bit Allows selection of high impedance output P channel open drain output N channel open drain output or CMOS output in...

Page 363: ...P11 OSC1 CLKIN I O Input output port High speed crystal ceramic oscillation pin external clock input pin 18 2 Description of Registers 18 2 1 List of Registers Address H Name Symbol Byte Symbol Word R...

Page 364: ...ut level of the Port 1 In output mode the value of this register is output to the Port 1 pin The value written to P1D is readable In input mode the input level of the Port 1 pin is read when P1D is re...

Page 365: ...R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 P0DIR is a special function register SFR to select the input output mode of Port 0 Description of Bits P11 10DIR bits 1 to 0 The P11 1...

Page 366: ...MOS output in output mode and to select high impedance input input with a pull down resistor or input with a pull up resistor in input mode Setting of P10 pin Description P10C1 P10C0 When output mode...

Page 367: ...CON1 At a system reset high impedance output mode is selected as the initial state In output mode L or H level is output to each pin of Port 1 depending on the value set by the Port 1 data register P1...

Page 368: ...Chapter 19 Port2...

Page 369: ...nput with a pull down resistor or input with a pull up resistor for each bit in input mode External interrupt inputs EXI20 EXI21 EXI22 EXI23 the SA ADC inputs AIN4 AIN5 AIN6 AIN7 RC ADC channel 1 osci...

Page 370: ...EXI21 AIN5 CS1 SINF0 TXDF0 I O Input output port External interrupt SA ADC AIN5 Reference capacitor connection pin for RC ADC CS1 SSIOF data input SINF0 UARTF data output TXDF0 P22 EXI22 AIN6 RS1 SCKF...

Page 371: ...egisters Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F220 Port 2 data register P2D R W 8 00 0F221 Port 2 direction register P2DIR R W 8 00 0F222 Port 2 control register P2CON0 P2C...

Page 372: ...ut level of the Port 2 pin is read when P2D is read Output mode or input mode is selected by using the port mode register P2DIR described later Description of Bits P23 20D bits 3 to 0 The P23 20D bits...

Page 373: ...0 0 0 P2DIR is a special function register SFR to select the input output mode of Port 2 Description of Bits P23 20DIR bits 3 to 0 The P23 20DIR pins are used to set the input output direction of the...

Page 374: ...down resistor or input with a pull up resistor in input mode Setting of P20 pin When output mode is selected P20DIR bit 0 When input mode is selected P20DIR bit 1 P20C1 P20C0 Description 0 0 High imp...

Page 375: ...cted P23DIR bit 0 When input mode is selected P23DIR bit 1 P23C1 P23C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down r...

Page 376: ...pin P20MD1 P20MD0 Description 0 0 General purpose input output mode External interrupt initial value 0 1 RC oscillation waveform input pin for RC AD IN1 1 0 SSIOF data output SOUTF0 1 1 UARTF data inp...

Page 377: ...surement for RC ADC RT1 1 0 SSIOF enable input output SSF0 1 1 FTM output mode TMOUT3 Note If any bit combination out of the above is set to Prohibited and the corresponding bit of the Port 2 is speci...

Page 378: ...et by the Port 2 data register P2D In input mode the input level of each pin of Port 2 can be read from the Port 2 data register P2D 19 3 2 Primary Function except for Input Output Port Port 2 is assi...

Page 379: ...Chapter 20 Port 3...

Page 380: ...nterface MELODY Chapter 23 Melody Driver SA ADC Chapter 25 Successive approximate type A D converter COMP Chapter 26 Analog Comparator 20 1 1 Features Allows selection of high impedance output P chann...

Page 381: ...RT with FIFO TXDF0 Output for SSIO SCK0 SOUT0 Output for SSIO with FIFO SCKF0 SOUTF0 Output for I2 C bus SDA0 1 SCL0 1 Timer out output TMOUT4 5 6 7 Buzzer output MD0 P30 to P37 P3DIR P3MOD P3CON VDD...

Page 382: ...l interrupt Comparator side input 1 Melody Buzzer output MD0 FTM output TMOUT5 P34 EXI34 AIN0 SDA1 SOUTF0 RXDF0 I O I O port External interrupt Successive approximation type A D converter input AIN0 I...

Page 383: ...egisters Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F228 Port 3 data register P3D R W 8 00 0F229 Port 3 direction register P3DIR R W 8 00 0F22A Port 3 control register P3CON0 P3C...

Page 384: ...later Description of Bits P37 30D bits 7 to 0 The P37 30D bits are used to set the output value of the Port 3 pin in output mode and to read the pin level of the Port 3 pin in input mode P30D Descript...

Page 385: ...ML620Q503 Q504 User s Manual Chapter 20 Port 3 FEUL620Q504 20 6 P37D Description 0 Output or input level of the P37 pin L 1 Output or input level of the P37 pin H...

Page 386: ...DIR bits 7 to 0 The P37 30DIR bits are used to set the input output mode of the port 3 pin P30DIR Description 0 P30 pin Output initial value 1 P30 pin Input P31DIR Description 0 P31 pin Output initial...

Page 387: ...Q504 20 8 Note The P34 to P37 pins are assigned to successive approximation type A D converter input or comparator input If it is used as a successive approximation type A D converter input or compara...

Page 388: ...impedance output P channel open drain output N channel open drain output or CMOS output in output mode and to select high impedance input input with a pull down resistor or input with a pull up resist...

Page 389: ...ected P34DIR bit 0 When input mode is selected P34DIR bit 1 P34C1 P34C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down...

Page 390: ...mpedance input 0 1 P channel open drain output Input with a pull down resistor 1 0 N channel open drain output Input with a pull up resistor 1 1 CMOS output High impedance input Note The P34 to P37 pi...

Page 391: ...y tertiary or quartic function of the port 3 Description of Bits P30MD1 0 bits 8 0 The P30MD1 0 bits are used to select the primary secondary tertiary or quartic function of the P30 pin P30MD1 P30MD0...

Page 392: ...value 0 1 Buzzer output mode MD0 1 0 Prohibited 1 1 FTM output mode TMOUT5 P34MD1 0 bits 12 4 The P34MD1 0 bits are used to select the primary secondary tertiary or quartic function of the P34 pin P34...

Page 393: ...rohibited 1 0 Synchronous serial port with FIFO chip select input output mode SSF0 1 1 FTM output mode TMOUT7 Note When the pin is set to Prohibited and the output mode is selected by the Port 3 contr...

Page 394: ...he Port 3 data register P3D 20 3 2 Primary Function Other Than Input Output Port The successive approximation type A D converter input AIN0 to AIN3 comparator input CMP0P M CMP1P M or external interru...

Page 395: ...Chapter 21 Port 4...

Page 396: ...th FIFO I2 C Chapter 15 I2 C Bus Interface MELODY Chapter 23 Melody Driver 21 1 1 Features Direct LED drive is available Allows selection of high impedance output P channel open drain output N channel...

Page 397: ...for UART TXD0 Output for UART with FIFO TXDF0 Output for SSIO SCK0 SOUT0 Output for SSIO with FIFO SCKF0 SOUTF0 Output for I2 C bus SDA0 1 SCL0 1 Timer out output TMOUT8 9 A B Comparator output CMP0...

Page 398: ...put SCK0 FTM output TMOUT8 P43 EXI43 MD0 TMOUT9 I O I O port External interrupt Melody Buzzer output MD0 FTM output TMOUT9 P44 EXI44 SDA1 SOUTF0 RXDF0 I O I O port External interrupt I 2 C data I O SD...

Page 399: ...egisters Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F230 Port 4 data register P4D R W 8 00 0F231 Port 4 direction register P4DIR R W 8 00 0F232 Port 4 control register P4CON0 P4C...

Page 400: ...later Description of Bits P47 40D bits 7 to 0 The P47 40D bits are used to set the output value of the Port 4 pin in output mode and to read the pin level of the Port 4 pin in input mode P40D Descript...

Page 401: ...ML620Q503 Q504 User s Manual Chapter 21 Port 4 FEUL620Q504 21 6 P47D Description 0 Output or input level of the P47 pin L 1 Output or input level of the P47 pin H...

Page 402: ...40DIR bits 7 0 The P47 40DIR bits are used to set the input output mode of the port 4 pin P40DIR Description 0 P40 pin Output initial value 1 P40 pin Input P41DIR Description 0 P41 pin Output initial...

Page 403: ...impedance output P channel open drain output N channel open drain output or CMOS output in output mode and to select high impedance input input with a pull down resistor or input with a pull up resis...

Page 404: ...cted P44DIR bit 0 When input mode is selected P44DIR bit 1 P44C1 P44C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down r...

Page 405: ...ected P47DIR bit 0 When input mode is selected P47DIR bit 1 P47C1 P47C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down...

Page 406: ...y tertiary or quartic function of the port 4 Description of Bits P40MD1 0 bits 8 0 The P40MD1 0 bits are used to select the primary secondary tertiary or quartic function of the P40 pin P40MD1 P40MD0...

Page 407: ...e 0 1 Melody Buzzer output mode MD0 1 0 Prohibited 1 1 FTM output mode TMOUT9 P44MD1 0 bits 12 4 The P44MD1 0 bits are used to select the primary secondary tertiary or quartic function of the P44 pin...

Page 408: ...n of the P47 pin P47MD1 P47MD0 Description 0 0 General purpose input output mode External interrupt mode initial value 0 1 High speed clock output mode OUTCLK 1 0 Synchronous serial port with FIFO chi...

Page 409: ...register P4D In input mode the input level of each pin of Port 4 can be read from the Port 4 data register P4D 21 3 2 Primary Function Other Than Input Output Port The external interrupt input EXI40 t...

Page 410: ...Chapter 22 Port 5...

Page 411: ...IFO I2 C Chapter 15 I2 C Bus Interface MELODY Chapter 23 Melody Driver 22 1 1 Features Direct LED drive is available Allows selection of high impedance output P channel open drain output N channel ope...

Page 412: ...Output for UART with FIFO TXDF0 Output for SSIO SCK0 SOUT0 Output for SSIO with FIFO SCKF0 SOUTF0 Output for I2 C bus SDA0 1 SCL0 1 Timer out output TMOUTC D E F Low sped clock output LSCLKO High spe...

Page 413: ...TMOUTC P53 EXI53 LED MD0 TMOUTD I O I O port External interrupt LED direct drive Melody Buzzer output MD0 FTM output TMOUTD P54 EXI54 SDA1 SOUTF0 RXDF0 I O I O port External interrupt I 2 C data I O S...

Page 414: ...egisters Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F238 Port 5 data register P5D R W 8 00 0F239 Port 5 direction register P5DIR R W 8 00 0F23A Port 5 control register P5CON0 P5C...

Page 415: ...later Description of Bits P57 50D bits 7 to 0 The P57 50D bits are used to set the output value of the Port 5 pin in output mode and to read the pin level of the Port 5 pin in input mode P50D Descript...

Page 416: ...ML620Q503 Q504 User s Manual Chapter 22 Port 5 FEUL620Q504 22 6 P57D Description 0 Output or input level of the P57 pin L 1 Output or input level of the P57 pin H...

Page 417: ...DIR bits 7 to 0 The P57 50DIR bits are used to set the input output mode of the port 5 pin P50DIR Description 0 P50 pin Output initial value 1 P50 pin Input P51DIR Description 0 P51 pin Output initial...

Page 418: ...er 22 Port 5 FEUL620Q504 22 8 Note The P50 to P57 pins are assigned to successive approximation type A D converter input If it is used as a successive approximation type A D converter input set the ap...

Page 419: ...impedance output P channel open drain output N channel open drain output or CMOS output in output mode and to select high impedance input input with a pull down resistor or input with a pull up resis...

Page 420: ...ected P54DIR bit 0 When input mode is selected P54DIR bit 1 P54C1 P54C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down...

Page 421: ...initial value High impedance input 0 1 P channel open drain output Input with a pull down resistor 1 0 N channel open drain output Input with a pull up resistor 1 1 CMOS output High impedance input No...

Page 422: ...y tertiary or quartic function of the port 5 Description of Bits P50MD1 0 bits 8 0 The P50MD1 0 bits are used to select the primary secondary tertiary or quartic function of the P50 pin P50MD1 P50MD0...

Page 423: ...value 0 1 Buzzer output mode MD0 1 0 Prohibited 1 1 FTM output mode TMOUTD P54MD1 0 bits 12 4 The P54MD1 0 bits are used to select the primary secondary tertiary or quartic function of the P54 pin P54...

Page 424: ...n of the P57 pin P57MD1 P57MD0 Description 0 0 General purpose input output mode External interrupt mode initial value 0 1 High speed clock output mode OUTCLK 1 0 Synchronous serial port with FIFO chi...

Page 425: ...ister P5D In input mode the input level of each pin of Port 5 can be read from the Port 5 data register P5D 22 3 2 Primary Function Other Than Input Output Port The external interrupt input EXI50 to E...

Page 426: ...Chapter 23 Melody Driver...

Page 427: ...es 8 frequencies and 15 duty levels 7 duty levels when buzzer frequency 4 096kHz are available 23 1 2 Configuration Figure 23 1 shows the configuration of the melody driver MD0CON Melody 0 control reg...

Page 428: ...Registers 23 2 1 List of Registers Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F8C0 Melody 0 control register MD0CON R W 8 00 0F8C1 Melody 0 tempo code register MD0TMP R W 8 00 0F...

Page 429: ...R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 MD0CON is a special function register SFR to control the melody and the buzzer Description of Bits M0RUN bit 0 The M0RUN bit is used to control start...

Page 430: ...veform type in the buzzer mode Description of Bits M0TM3 0 bits 3 to 0 When melody mode is selected BZMD bit 0 M0TM3 M0TM2 M0TM1 M0TM0 Description 0 0 0 0 480 initial value 0 0 0 1 480 0 0 1 0 320 0 0...

Page 431: ...0 0 MD0TL is a special function register SFR to set the scale code and tone length of a melody when melody mode is selected and a buzzer output frequency and duties when buzzer mode is selected Descri...

Page 432: ...equency 4 096kHz Buzzer frequency 4 096kHz 0 0 0 0 1 8 DUTY initial value 1 16 DUTY initial value 0 0 0 1 1 8DUTY 1 16DUTY 0 0 1 0 1 8DUTY 2 16DUTY 0 0 1 1 1 8DUTY 3 16DUTY 0 1 0 0 2 8DUTY 4 16DUTY 0...

Page 433: ...red The melody 0 signal output pin MD0 is assigned as the secondary function of Port 3 or Port 4 or Port 5 For the secondary function of Port 3 or Port 4 or Port 5 see Chapter 20 Port 3 or Chapter 21...

Page 434: ...le 23 1 Note Codes of Melody Examples Note Note code MD0LEN MD0TON Hexade cimal 5 4 3 2 1 0 6 5 4 3 2 1 0 G 2 1 0 1 1 1 1 0 1 0 1 0 0 1 2F29H D 2 0 0 1 1 1 1 0 1 1 0 1 1 0 0F36H G 2 0 0 1 1 1 1 0 1 0...

Page 435: ...when all the bits are set to 0 is equal to the shortest tone length the tempo when the only M0TP0 bit is set to 1 Table 23 2 Correspondence between Tempos and Tempo Codes Tempo Tempo code MD0TMP M0TP...

Page 436: ...M0LN4 M0LN3 M0LN2 M0LN1 M0LN1 M0LN5 0 1 1 1 1 1 1 3FH 1 0 1 1 1 1 2FH 0 1 1 1 1 1 1FH 0 1 0 1 1 1 17H 0 0 1 1 1 1 0FH 0 0 1 0 1 1 0BH 0 0 0 1 1 1 07H 0 0 0 1 0 1 05H 0 0 0 0 1 1 03H 0 0 0 0 1 0 02H 0...

Page 437: ...des Scale Frequency Hz Scale code MD0TON M0TN6 M0TN5 M0TN4 M0TN3 M0TN2 M0TN1 M0TN0 M0TN6 0 C 1 529 1 1 1 1 0 1 1 7BH Cis 1 560 1 1 1 0 1 0 0 74H D 1 590 1 1 0 1 1 1 0 6EH Dis 1 624 1 1 0 1 0 0 0 68H E...

Page 438: ...utput frequency in the melody 0 scale code register MD0TON 5 When the M0RUN bit of the melody 0 control register MD0CON is set to 1 the waveform equivalent to the buzzer sound that is set from the MD0...

Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...

Page 440: ...asurement at two points For input clocks see Chapter 6 Clock Generation Circuit 24 1 1 Features 2 channel system by time division 24 1 2 Configuration The RC ADC consists of two RC oscillator circuits...

Page 441: ...ection pin RCT0 O Pin for connection with a resistive capacitive sensor for measurement on Channel 0 RT0 O Pin for connection with a resistive sensor for measurement on Channel 0 RCM O RC oscillation...

Page 442: ...RADCA0 R W 8 16 00 0F801 RADCA0H R W 8 00 0F802 RC ADC counter A register 1 RADCA1L RADCA1 R W 8 16 00 0F803 RADCA1H R W 8 00 0F804 RC ADC counter B register 0 RADCB0L RADCB0 R W 8 16 00 0F805 RADCB0...

Page 443: ...C ADC Counter A Register 1 RADCA1 Address 0F802H Access R W Access size 8 16 bits Initial value 0000H 7 6 5 4 3 2 1 0 RADCA1L RAA23 RAA22 RAA21 RAA20 RAA19 RAA18 RAA17 RAA16 R W R W R W R W R W R W R...

Page 444: ...C ADC Counter B Register 1 RADCB1 Address 0F806H Access R W Access size 8 16 bits Initial value 0000H 7 6 5 4 3 2 1 0 RADCB1L RAB23 RAB22 RAB21 RAB20 RAB19 RAB18 RAB17 RAB16 R W R W R W R W R W R W R...

Page 445: ...ts OM3 0 bits 3 to 0 The OM3 0 bits are used to select an oscillation mode for the RC oscillator circuits OM3 OM2 OM1 OM0 Description 0 0 0 0 IN0 pin external clock input mode initial value 0 0 0 1 RS...

Page 446: ...er FEUL620Q504 24 7 RACK2 0 bits 7 to 5 The RACK2 0 bits are used to select the base clock of Counter A BSCLK RACK2 RACK1 RACK0 Description 0 0 0 LSCLK initial value 0 0 1 OSCLK 0 1 0 1 2OSCLK 0 1 1 1...

Page 447: ...ister SFR used to control A D conversion operation of the RC ADC Description of Bits RARUN bit 0 The RARUN bit is used to start or stop A D conversion of the RC ADC Set RARUN to 1 to start the A D con...

Page 448: ...is selected by setting RADI to 1 The RARUN bit of the RC ADC control register RADCON is used to start or stop RC ADC conversion operation When RARUN is set to 0 the oscillator circuits stop so that co...

Page 449: ...0 0 0 1 1 0 Z Z 0 1 Z Z Z RS0 CS0 oscillation RCOSC0 oscillation mode 2 0 0 1 0 Z 1 0 Z 0 1 Z Z Z RT0 CS0 oscillation 3 0 0 1 1 Z Z 1 0 0 1 Z Z Z RT0 1 CS0 oscillation 4 0 1 0 0 1 0 Z 0 1 Z Z Z Z RS0...

Page 450: ...ured as secondary function input or output using the mode register P0MOD0 P0MOD1 P2MOD0 P2MOD1 of the corresponding port All the Port 3 pins except P05 RCM see Section 24 1 3 List of Pins are configur...

Page 451: ...OM3 OM2 OM1 OM0 oscillation mode 0 0 0 1 Oscillates with the reference resistor RS0 and CS0 0 0 1 0 Oscillates with the sensor RT0 and CS0 0 0 1 1 Oscillates with the reference resistor RT0 1 and CS0...

Page 452: ...nverter FEUL620Q504 24 13 OM3 OM2 OM1 OM0 oscillation mode 0 1 0 1 Oscillates with the reference resistor RS1 and CS1 0 1 1 0 Oscillates with the sensor RT1 and CS1 Figure 24 5 When RCOSC1 Is Used for...

Page 453: ...1 the value obtained by subtracting the count value nA0 from the maximum value 1 1000000H The product of the count value nA0 and the BSCLK clock cycle indicates the gate time kPreset 000000H in Counte...

Page 454: ...et the RADI bit of RADMOD to 1 to specify generating of an interrupt request signal by Counter B overflow nSet the RARUN bit of RADCON to 1 to start A D conversion When the RARUN bit is set to 1 and t...

Page 455: ...tRCCLK and is expressed by the following expression nA1 nB1 tRCCLK 1 tBSCLK fRCCLK That is nA1 is a value inversely proportional to the RC oscillation frequency fRCCLK Figure 24 7 Operation Timing in...

Page 456: ...nT0 K RT0 K f T Figure 24 9 Temperature Characteristics of Thermistor Figure 24 10 A D Conversion Characteristics Ideal characteristics when nT0 is proportional to RT0 RT0 is expressed as a function o...

Page 457: ...using these resistances will be like the solid lines in Figures 24 12 and 24 13 however in reality it would appear that they will be like the dotted lines due to error factors such as IC temperature c...

Page 458: ...the operation time gate time for the second step fluctuates depending on the value of thermistor RT0 To avoid the fluctuation of the operation time using a method that uses the following combination i...

Page 459: ...ignal is set to 1 and an RC ADC interrupt request is generated Section a Also the generation of interrupt request releases HALT mode section b and at the same time A D conversion operation stops Secti...

Page 460: ...period is expressed by tRCCLK kRCCLK x R x C tRCCLK RS0 and tRCCLK RT0 are expressed by the following expressions tRCCLK RS0 kRCCLK CS0 CVR RS0 Expression E tRCCLK RT0 kRCCLK CS0 CVR RT0 When express...

Page 461: ...hermistor and the oscillation frequency can be measured For instance the coefficient for conversion from the above described nA1 value to a temperature indication value can be obtained by checking the...

Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...

Page 463: ...start the A D conversion using the timer trigger mode Touch sensor supported 25 1 2 Configuration Figure 25 1 shows the configuration of SA ADC SADRn SA ADC result register n SADCON0 1 SA ADC control...

Page 464: ...s P20 pin primary function P21 AIN5 I Successive approximation type A D converter input pin 5 Use as P21 pin primary function P22 AIN6 I Successive approximation type A D converter input pin 6 Use as...

Page 465: ...C SA ADC result register 6 SADR6L SADR6 R 8 16 00 0F82D SADR6H R 8 00 0F82E SA ADC result register 7 SADR7L SADR7 R 8 16 00 0F82F SADR7H R 8 00 0F830 SA ADC result register 8 SADR8L SADR8 R 8 16 00 0F...

Page 466: ...8L SADR8 0F831H SADR8H 0F832H SADR9L SADR9 0F833H SADR9H 0F834H SADRAL SADRA 0F835H SADRAH 0F836H SADRBL SADRB 0F837H SADRBH Access R Access size 8 16 bits Initial value 0000H 7 6 5 4 3 2 1 0 SADRnL S...

Page 467: ...nable register SADEN Consecutive A D conversion cannot be used in the trigger mode SAST0 bit of SADTRG register is 1 Therefore set SALP to 0 SALP Description 0 Single A D conversion only initial value...

Page 468: ...Hz when OSCLK is selected or 32 768kHz when the low speed clock is selected This counter is designed to have an optimal conversion time for 4MHz when OSCLK is selected or 32 768kHz when LSCLK is selec...

Page 469: ...t this bit to 1 to start the A D conversion and 0 to stop it When SALP is 0 and then A D conversion on the channel with the largest channel number among the selected ones is terminated the SARUN bit i...

Page 470: ...W R W R W R W Initial value 0 0 0 0 0 0 0 0 SADEN is a special function register SFR used to choose A D conversion channel s Description of Bits SACHn bit 11 to 0 The SACHn bits are used to select cha...

Page 471: ...13 12 11 10 9 8 SADTCHH SATCHB SATCHA SATCH9 SATCH8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 SADTCH is a special function register SFR used to select channels to be operated i...

Page 472: ...0 SADTRG is a special function register SFR used to select the external trigger for the A D conversion Description of Bits SAST0 bit 0 Selects the A D conversion start mode SAST0 Description 0 Normal...

Page 473: ...0 1 0 1 TM5INT 0 0 1 1 0 TM6INT 0 0 1 1 1 TM7INT 0 1 Setting prohibited 1 0 0 0 0 FTM0TGO 1 0 0 0 1 FTM1TGO 1 0 0 1 0 FTM2TGO 1 0 0 1 1 FTM3TGO 1 0 1 Setting prohibited 1 1 Setting prohibited Note Th...

Page 474: ...R W Initial value 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 SADCVTH SAPCT4 SAPCT3 SAPCT2 SAPCT1 SAPCT0 SACPT2 SACPT1 SACPT0 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 SADCVT is a s...

Page 475: ...ADC operation 0 0 0 No operation 0 0 1 No operation 0 1 0 Non touch sensor mode 0 1 1 No operation 1 0 0 No operation 1 0 1 No operation 1 1 0 No operation 1 1 1 Touch sensor mode Do not start the A...

Page 476: ...on termination interrupt SADINT is generated 2 Trigger mode 1 Wait until the oscillation of the clock used for the A D conversion is started and stabilized When LSCLK is selected it is revealed that t...

Page 477: ...et to 1 then the bit 0 SARUN of the SA ADC control register 1 SADCON1 to 1 the SA ADC circuit starts operating The touch sensor supported A D conversion is performed on the channels selected in the SA...

Page 478: ...ed by the voltage input from AINn n 0 to 11 It is possible to charge it by connecting an external capacitor of 0 47uF or more regardless of the input impedance Figure 25 5 shows the connection of SA A...

Page 479: ...Chapter 26 Analog Comparator...

Page 480: ...28 125kHz OSCLK 16MHz OSCLK 64 250kHz OSCLK 16MHz The last status of comparator output CMPnD remains after the comparator is deactivated Single mode is available 26 1 2 Configuration Figure 26 1 shows...

Page 481: ...s H Name Symbol Byte Symbol Word R W Size Initial value H 0F920 Comparator 0 control register CMP0CON R W 8 00 0F922 Comparator 0 mode register CMP0MODL CMP0MOD R W 8 16 00 0F923 CMP0MODH R W 8 00 0F9...

Page 482: ...ivates the Comparator n measurement is stopped initial value 1 Activates the Comparator n measurement is in progress CMPnD bit 1 The CMPnD bit indicates the status of comparator n output CMPnOUT shown...

Page 483: ...ed to set comparator judge interrupt generation condition Each function mode has different interrupt generation sources CMPnMD CMPnE1 CMPnE0 Description Single mode 0 Generate interrupt when CMPnD is...

Page 484: ...MPnCK CMPnSM1 0 bit 12 9 to 8 Set comparator control clock and sampling interval timing for filtering Sampling is always disabled regardless of sampling setting during the STOP mode CMPnCK CMPnSM1 CMP...

Page 485: ...measurement or CMPnD is changed from 0 to 1 during measurement 01 L interrupt Generate interrupt when CMPnD is 0 CMPnD is 0 when starting measurement or CMPnD is changed from 1 to 0 during measurement...

Page 486: ...y by hardware Setting instruction 1 Set Operating clock filtering interrupt option and single mode by CMPnMOD register CMPnE1 0 Description 00 Generate interrupt when CMPnD is 0 01 10 Generate interru...

Page 487: ...rdy time to judge interrupt Trdy Tend time to comparator off 0 0 0 Low speed LSCLK 32 768kHz No filtering 2 61 0 us 3 91 6 us 0 0 1 T16KHZ LTBC output 1 2 of LSCLK 3 183 1 us 4 244 2 us 1 0 0 High spe...

Page 488: ...sult from software CMPnD Compare result is kept until 1 is set to CMPnEN It is prohibited switch to STOP mode during operation CMPnEN need to be 0 when switch to STOP mode The timing chart is as follo...

Page 489: ...Chapter 27 Flash Memory Control...

Page 490: ...or the rewriting conditions and specifications refer to the section for flash memory specification in Appendix C Electrical Characteristics For the program memory space and data flash area refer to Ch...

Page 491: ...al value H 0F0E0 Flash address register FLASHAL FLASHA R W 8 16 00 0F0E1 FLASHAH R W 8 00 0F0E2 Flash data register FLASHDL FLASHD R W 8 16 00 0F0E3 FLASHDH R W 8 00 0F0E4 Flash control register FLASH...

Page 492: ...et the flash memory rewrite addresses Description of Bits FA15 0 bits 15 to 0 The FA15 to FA0 bits are used to set the address for block erase sector erase or 1 word write The bit 0 is fixed to 0 and...

Page 493: ...R W Initial value 0 0 0 0 0 0 0 0 FLASHD is a special function register SFR used to set the flash memory rewrite data Description of Bits FD7 0 bits 7 to 0 The FD7 to FD0 bits are used to set the low...

Page 494: ...mory rewrite Description of Bits FERS bit 0 The FERS bit is used to start the block erase Setting the FERS bit to 1 erases the block specified by the FLASHSEG and FLASHAH registers This bit is automat...

Page 495: ...ables a one time block erase or sector erase or 1 word write For subsequent block erase or sector erase or 1 word write it is necessary to write 0FAH and 0F5H to FLASHACP each time Even if another ins...

Page 496: ...0 FLASHSLF FSELF R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 FLASHSLF is a special function register SFR used to control the flash memory self rewrite function Description of Bi...

Page 497: ...and software interrupt vector area For the BRK instruction refer to nX U16 100 Core Instruction Manual Description of Bits REA15 12 bits 3 to 0 The REA15 to REA12 bits are used to set the higher 4 bi...

Page 498: ...ase time Max 100ms Block erase time Max 100ms 1 word 2 bytes write Max 40 s Note 1 ML620Q503 The test data area 0 7C00h to 0 7FFFh is excluded 2 ML620Q504 The test data area 0 FC00h to 0 FFFFh is excl...

Page 499: ...o 7 07FFH 1 1 1 0 0 0 0 0 0 0 0 Table 27 2 Address Setting Values for Sector Erase Area for sector erase FLASHSEG FLASHAH Segment Address SEG 2 SEG 1 SEG 0 FA 15 FA 14 FA 13 FA 12 FA 11 FA 10 FA 9 FA...

Page 500: ...Flash Rewrite Sequence 27 3 3 Program Memory Rewrite ISP Function The program can be rewritten by software by using the ISP function There are the following two ways to execute the ISP program 1 Exec...

Page 501: ...program separately from the normal interrupt Figure 27 2 shows a sample program for remap when the start address of the remap area is F000H Figure 27 3 shows the memory map before and after remapping...

Page 502: ...the boot program is normally placed startup boot from the ISP boot area can avoid a situation that recovery is not possible The boot program can rewrite the internal program of the LSI by using UART...

Page 503: ...gram after remapping Load address 0000H of ROM by startup of program executed after remapping at the head at which reset vector points and set it to stackpointer Figure 27 5 shows an example of progra...

Page 504: ...e flash write erase 2 1 word write LEA offset FLASHAH EA FLASHAH address MOV R0 0FAH Flash acceptor enable data MOV R1 0F5H Flash acceptor enable data MOV R2 02H Address increment data MOV R3 00H MOV...

Page 505: ...Chapter 28 Voltage Level Supervisor VLS...

Page 506: ...om 9 values 1 898V to 3 068V Can be used as voltage level detection reset VLS reset Can be used as voltage level detection interrupt VLS interrupt 28 1 2 Configuration The VLS consists of a comparator...

Page 507: ...n of Registers 28 2 1 List of Registers Address H Name Symbol Byte Symbol Word R W Size Initial value H 0F900 Voltage level supervisor control register VLSCONL VLSCON R W 8 16 00 0F901 VLSCONH R W 8 0...

Page 508: ...unction register SFR used to control the voltage level detector Description of Bits VLSLV3 0 bits 3 to 0 The VLSLV3 0 bits are used to select the VLS threshold voltage of fall VVLS The VLS has the hys...

Page 509: ...level detection flag It is 0 when the power supply voltage VDD is higher than the threshold voltage VVLS or 1 when the power supply voltage is lower than the threshold voltage VLSF is initialized to 0...

Page 510: ...0 Description of Bits VLSSEL1 0 bits 1 to 0 The VLSSEL1 0 bits are used to control enable disable of the VLS reset VLS interrupt request functions when the voltage is lower than the threshold voltage...

Page 511: ...9 The VLSAMD1 0 bits are used to set the VLS running mode VLSAMD1 VLSAMD0 Description 0 0 Use prohibit initial value 0 1 Use prohibit 1 0 Supervisor mode 1 1 Supervisor mode Note VLSAMD1 0 bits set t...

Page 512: ...voltage The VLS has a hysteresis charactristics HVLS The threshold voltage of rise is VVLS HVLS For detail see VLS characteristic in Appendix C The following operation mode are provided Supervisor mo...

Page 513: ...ltage a VLS interrupt or VLS reset is issued To turn off the VLS function set ENVLS to 0 from the software Figure 28 2 shows an example of the operation timing diagram when detecting without sampling...

Page 514: ...1 to issue a VLS reset because the VLS analog voltage is lower than the threshold voltage VVLS VDD returns to higher than the threshold voltage of rise VVLS HVLS Because it is judged that a VLS analo...

Page 515: ...evel detection flag VLSF is set to 1 to issue a VLS interrupt because VDD becomes lower than the specified threshold voltage VVLS The voltage level detection flag VLSF is set to 0 because VDD becomes...

Page 516: ...F is set to 1 to issue a VLS interrupt because the VLS analog voltage is lower than the threshold voltage VVLS VDD returns to higher than the threshold voltage of rise VVLS HVLS Because it is judged t...

Page 517: ...Chapter 29 LLD circuit...

Page 518: ...iption of resister Control LLD validation by resister setting LLD is invalidated initially LLD can be validated by setting block control resister 45 BLKCON45 DLLD bit to 0 29 3 Description of operatio...

Page 519: ...Chapter 30 On Chip Debug Function...

Page 520: ...SE User s Manual Figure 30 1 Connection to On chip Debug Emulator uEASE Note Please do not apply LSIs used for debugging to mass production When using the on chip debug function or the flash rewrite f...

Page 521: ...rom the on chip debug emulator uEASE For more details on the on chip debug emulator see uEASE User s Manual Table 30 1 shows the Flash memory rewrite functions Table 30 1 Flash Memory Rewrite Function...

Page 522: ...Appendixes...

Page 523: ...IE4 IE45 R W 8 16 00 0F015 IE5 R W 8 00 0F016 Interrupt enable register 67 IE6 IE67 R W 8 16 00 0F017 IE7 R W 8 00 0F018 Interrupt request register 01 IRQ0 IRQ01 R W 8 16 00 0F019 IRQ1 R W 8 00 0F01A...

Page 524: ...frequency adjustment register LTBADJL LTBADJ R W 8 16 00 0F063 LTBADJH R W 8 00 0F064 Low speed time base counter interrupt select register LTBINTL LTBINT R W 8 16 30 0F065 LTBINTH R W 8 06 0F068 Bloc...

Page 525: ...register P4CON0 P4CON R W 8 16 00 0F233 P4CON1 R W 8 00 0F234 Port 4 mode register P4MOD0 P4MOD R W 8 16 00 0F235 P4MOD1 R W 8 00 0F238 Port 5 data register P5D R W 8 00 0F239 Port 5 direction regist...

Page 526: ...ster FT0CLKL FT0CLK R W 8 16 00 0F40F FT0CLKH R W 8 00 0F410 FTM0 trigger register 0 FT0TRG0L FT0TRG0 R W 8 16 00 0F411 FT0TRG0H R W 8 00 0F412 FTM0 trigger register 1 FT0TRG1L FT0TRG1 R W 8 16 00 0F4...

Page 527: ...R W 8 16 00 0F451 FT2TRG0H R W 8 00 0F452 FTM2 trigger register 1 FT2TRG1L FT2TRG1 R W 8 16 00 0F453 FT2TRG1H R W 8 00 0F458 FTM2 interrupt enable register FT2INTEL FT2INTE R W 8 16 00 0F459 FT2INTEH...

Page 528: ...ansmit receive buffer SIO0BUFL SIO0BUF R W 8 16 00 0F701 SIO0BUFH R W 8 00 0F702 Serial port 0 control register SIO0CON R W 8 00 0F704 Serial port 0 mode register SIO0MOD0 SIO0MOD R W 8 16 00 0F705 SI...

Page 529: ...0 0F78E SIOF0 write data register SF0DWRL SF0DWR R W 8 16 00 0F78F SF0DWRH R W 8 00 0F790 SIOF0 read data register SF0DRRL SF0DRR R 8 16 00 0F791 SF0DRRH R 8 00 0F7C0 UARTF0 transmit receive buffer UA...

Page 530: ...8 00 0F832 SA ADC result register 9 SADR9L SADR9 R 8 16 00 0F833 SADR9H R 8 00 0F834 SA ADC result register A SADRAL SADRA R 8 16 00 0F835 SADRAH R 8 00 0F836 SA ADC result register B SADRBL SADRB R 8...

Page 531: ...ame Symbol Byte Symbol Word R W Size Initial value H 0F922 Comparator 0 mode register CMP0MODL CMP0MOD R W 8 16 00 0F923 CMP0MODH R W 8 00 0F928 Comparator 1 control register CMP1CON R W 8 00 0F92A Co...

Page 532: ...or Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow and humidity absorbed in storage Therefore before you perform reflow mounting contact...

Page 533: ...ply voltage 1 VDD Ta 25 C 0 3 to 4 6 V Power supply voltage 2 VDDL Ta 25 C 0 3 to 2 0 V Power supply voltage 3 VDDX Ta 25 C 0 3 to 2 0 V Input voltage VIN Ta 25 C 0 3 to VDD 0 3 V Output voltage VOUT...

Page 534: ...itor 2 CDL Using DT 26 from Daishinku 12 to 16 pF CGL 12 to 16 Low speed crystal 1 oscillation external capacitor 3 CDL Using VT 200 F from SII 12 to 22 pF CGL 12 to 22 High speed crystal Ceramic osci...

Page 535: ...ting temperature Ambience TOP Data area write erase 40 to 85 C Program area write erase 0 to 40 C Operating voltage Write time VDD Write erase 1 8 to 3 6 V CEPD Data area 1 024B x 2 10 000 times CEPP...

Page 536: ...rt time TXTL 2 s 1 High speed crystal oscillation start time TXTH 20 ms Low speed built in RC oscillation frequency 1 2 fLCR Ta 25 C typ 1 5 32 768 typ 1 5 kHz Ta 40 to 85 C typ 5 32 768 typ 5 High sp...

Page 537: ...speed crystal oscillating 32 768kHz High speed oscillation is stopped Ta 25 C 2 2 7 A Ta 40 to 85 C 18 Power consumption 4 IDD4 CPU Low speed 2 5 Low speed built in CR oscillating High speed oscillati...

Page 538: ...9H 2 505 2 605 2 705 vlscon AH 2 700 2 800 2 900 vlscon BH 2 968 3 068 3 168 VVLS Hysteresis width VDD rise HVLS VVLS X 1 8 VVLS X 3 8 VVLS X 6 3 V DC characteristics LLD VDD 1 8 to 3 6V VSS 0V Ta 40...

Page 539: ...4 Output voltage 2 P40 P41 P52 P53 LED mode is selected VOL2 2 7V VDD 3 6V IOL 5 0mA 0 6 1 8V VDD 2 7V IOL 2 0mA 0 4 Output voltage 3 P30 P31 P34 P35 P40 P41 P44 P45 P50 P51 P54 P55 I 2 C mode is sele...

Page 540: ...IIL1 VIL1 VSS 900 300 20 Input current 2 TEST0 IIH2 VIH2 VDD 20 300 900 IIL2 VIL2 VSS 1 Input current 3 PXT0 PXT1 P00 P05 P20 P23 P30 P37 P40 P47 P50 P57 IIH3 VIH3 VDD at pull down 1 15 200 IIL3 VIL3...

Page 541: ...ise specified Parameter Symbol Condition Rating Unit Measuring circuit Min Typ Max Input voltage 1 RESET_N TEST0 TEST1_N PXT0 PXT1 P00 P05 P10 P11 P20 P23 P30 P37 P40 P47 P50 P57 VIH1 0 7 VDD VDD V 5...

Page 542: ...ermine the specified measuring conditions 2 Measured at the specified output pins 2 1 VDD VREF VDDL VSS VDDX VDD VREF VDDX CX CV 32 768kHz Crystal Oscillator CGL CDL XT0 OSC0 VSS CV 1 0 F CL 2 2 F CX...

Page 543: ...g circuit 3 Measuring circuit 4 Input pins A Output pins 3 Measured at the specified output pins 3 VDD VREF VDDL VSS VDDX Input pins A VIH VIL Output pins 1 Input logic circuit to determine the specif...

Page 544: ...nual Appendix C Electrical Characteristics FEUL620Q504 C 1 Measuring circuit 5 Input pins VIH VIL Output pins 1 Input logic circuit to determine the specified measuring conditions 1 Waveform monitorin...

Page 545: ...DD 1 8 to 3 6V VSS 0V Ta 40 to 85 C unless otherwise specified Parameter Symbol Condition Rating Unit Min Typ Max External interrupt disable period tNUL Interruput enable MIE 1 CPU NOP operation 2 5 x...

Page 546: ...slave mode tSW High speed oscillation is not active 4 s High speed oscillation is active 200 ns SCK output pulse width master mode tSW tSCYC 0 4 tSCYC 0 5 tSCYC 0 6 s SOUT output delay time slave mod...

Page 547: ...tSU DAT 0 25 s SCL setup time stop condition tSU STO 4 0 s Bus free time tBUF 4 7 s AC characteristics I2 C bus interface fast mode 400kHz VDD 1 8 to 3 6V VSS 0V Ta 40 to 85 C unless otherwise specifi...

Page 548: ...n fOSCX RS0 CS0 oscillation fOSCX RS1 CS1 oscillation x 1 2 3 Measuring circuit Note Please have the shortest layout for the common node wiring patterns which are connected to the external capacitors...

Page 549: ...2 2V using Low speed clock 10 10 Differential non linearity error DNL 2 7V VREF 3 6V 3 3 2 2V VREF 2 7V 5 5 1 8V VREF 2 2V using Low speed clock 9 9 Zero scale error VOFF 2 2V VREF 3 6V 6 6 1 8V VREF...

Page 550: ...ix C Electrical Characteristics FEUL620Q504 C 7 Power on and shutdown Procedures In case of power on or shutdown of VDD the procedures and constraints are shown as following VDD 30mV or less over 2sec...

Page 551: ...F RS0 RS1 10 K CS0 CS1 560 pF CVR0 CVR1 820 pF RT0 RT1 Thermistor 103AT Semitec XH NX8045GB 16 000MHz Nihon Denpa Kogyo XL DT 26 Daishinku P50 SDA P41 LED P51 SCL CDH P11 OSC1 XH RD 16MHz Xtal P33 MD0...

Page 552: ...Revision History...

Page 553: ...s Manual Revision History FEUL620Q504 R 1 Revision History Document No Date Page Description Previous Edition Current Edition PEUL620Q504 01 May 21 2014 Primary edition 1 0 FEUL620Q504 01 Apr 16 2015...

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