Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–14
12.2.7 SIOF0 Status Clear Register (SF0SRC)
Address: 0F78AH
Access: W
Access size: 8/16 bits
Initial value: 0000H
7 6 5 4 3 2 1 0
SF0SRCL
– – SF0SPIFC SF0MDFC SF0ORFC SF0FC SF0RFC SF0TFC
R/W W W W W W W W W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
SF0SRCH
SF0IRQ – – – – – – SF0WOFC
R/W W W W W W W W W
Initial value 0 0 0 0 0 0 0 0
SF0SRC is a special function register (SFR) used to clear the data transfer state and error state of the SSIOF.
Description of Bits
•
SF0TFC (bit 0)
SF0TFC clears the interrupt request of the transmission interrupt. The interrupt request is cleared by
writing "1". For the interrupt request, check on the SF0TFI bit of SF0SRR.
•
SF0RFC (bit 1)
SF0RFC clears the interrupt request of the receiving interrupt. The interrupt request is cleared by writing
"1". For the interrupt request, check on the SF0RFI bit of SF0SRR.
•
SF0FC (bit 2)
SF0FC clears the interrupt request of the transfer end interrupt. The interrupt request is cleared by
writing "1". For the interrupt request, check on the SF0FI bit of SF0SRR.
•
SF0ORFC (bit 3)
SF0ORFC clears the interrupt request of the overrun error flag. The interrupt request is cleared by
writing "1". For the interrupt request, check on the SF0ORF bit of SF0SRR.
•
SF0MDFC (bit 4)
SF0MDFC clears the interrupt request of the mode fault. The interrupt request is cleared by writing "1".
For the interrupt request, check on the SF0MDF bit of SF0SRR.
•
SF0SPIFC (bit 5)
SF0SPIFC clears the SSIOF1 byte (word) transfer end. The transfer end flag (SF0SPIF) is cleared by
writing "1".
•
SF0WOFC (bit 8)
SF0WOFC clears a write overflow. The write overflow flag (SF0WOF) is cleared by writing "1".
•
SF0IRQ (bit 15)
When there is any unprocessed interrupt source, the interrupt request is issued again by writing "1".