Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–25
5.2.11 Current Interrupt Request Level Register (CIL)
Address: 0F022H
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7 6 5 4 3 2 1 0
CILL CILN – – – CILM3 CILM2 CILM1 CILM0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
CILH – – – – – – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
The current interrupt request level register (CIL) indicates the interrupt level of the interrupt currently being
processed by the processor.
Access to this register is possible only when the interrupt level control is enabled by the ILEN register. If a
write/read access is made while the interrupt level control is disabled, a write access is ignored and a read access
reads either the value when the register was enabled or the initial value if the register has never been enabled.
When a "1" has been set in any bit position of CIL, the acceptance of interrupt requests is prohibited below the
interrupt level indicated by the highest order bit position set to "1". It indicates that the processing is being done
for an interrupt with the level corresponding to the bit position.
When "1"s have been set at several bit positions of CIL, it indicates that multiple interrupts are being processed.
<<Condition for setting>>
When the processor accepts an interrupt, "1" is set to the CILN bit if the interrupt request is non-maskable
interrupt. If the interrupt request is maskable interrupt, "1" is set to the bit position of CILM corresponding to the
level of the interrupt source.
<<Condition for clearing>>
When a write access is made, the highest order bit set to "1" is cleared. After the interrupt handler processing
is completed, execute a write access once.
Description of Bits
•
CILM3-0 (bits 3 to 0)
Indicates the level of the maskable interrupt request being processed by CPU.
CILM0 Description
0 Interrupt level 1 is not in processing (initial value)
1 Interrupt level 1 is in processing
CILM1 Description
0 Interrupt level 2 is not in processing (initial value)
1 Interrupt level 2 is in processing