ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–1
9 Function Timer (FTM)
9.1 General Description
FTM is a 16-bit multifunction timer with the capture and PWM functions in addition to the timer function. It can
be started/stopped using an external input signal and a signal from another timer as a trigger.
The LSI includes four channels of the multifunction timer.
9.1.1 Features
•
Equipped with the timer/capture/PWM functions using a 16-bit counter
•
1 to 64 dividing of LSCLK/OSCLK/HSCLK/external input selectable as timer clock
•
The timer output signal can be switched between the positive and negative logics
•
Duty interrupt and coincident interrupt with the setting value as well as the cyclic interrupt generated
•
Equipped with one-shot mode
•
An event trigger (external pin input interrupt or timer interrupt request) can control start/stop/clear of the
timer (however, the minimum pulse width of pin input is timer clock 3
φ
)
•
An external input can generate an emergency stop and emergency stop interrupt.
•
Two types of PWM with the same period and different duties and complementary PWM with the dead time
set can be output
•
The capture function can measure the duty/cycle of the input signal (41.6kHz at 128 resolution @ 16MHz
timer clock)
•
Interrupt source to be notified can be set
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...