Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 20 Port 3
FEUL620Q504 20–2
20.1.2 Configuration
Figure 20-1 shows the configuration of Port 3.
P3D : Port 3 data register
P3DIR : Port 3 direction register
P3CON : Port 3 control register
P3MOD : Port 3 mode register
Figure 20-1 Configuration of Port 3
Data bus
Output for UART (TXD0)
Output for UART with FIFO (TXDF0)
Output for SSIO (SCK0, SOUT0)
Output for SSIO with FIFO (SCKF0,SOUTF0)
Output for I
2
C bus (SDA0/1, SCL0/1)
Timer out output (TMOUT4/5/6/7)
Buzzer output (MD0)
P30 to P37
P3DIR
P3MOD,
P3CON
V
DD
V
DD
V
SS
V
SS
8
7
Port3
Output
Controller
P3D
V
DD
V
SS
Pull-up
Pull-down
Controller
Input for UART (RXD0)
Input for UART with FIFO (RXDF0)
Input for SSIO (SIN0)
Input for SSIO with FIFO (SINF0)
Input for I
2
C bus (SDA0/1)
3
8
EXI30 to EXI37
8
4
Input for successive approximation type
A/D (AIN0 to AIN3)
4
Comparator input
(CMP0P/M, CMP1P/M)