ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-1
4 Power Management
4.1 General Description
The LSI has four power management modes listed below to save the Power consumption.
It also has a block control function, which power downs the circuits of unused peripherals (reset registers and stop
clock supplies) to make even more reducing the current consumption.
(1)
HALT mode
(2)
HALT-H mode
(3)
DEEP-HALT mode
(4)
STOP mode
4.1.1 Features
•
HALT mode, where the CPU stops operating and only the peripheral circuit is operating
•
HALT-H mode, where the high-speed clock is automatically stopped when the CPU stops operating.
•
DEEP-HALT mode, where the CPU stops operating and only LTBC and timer can operate at lower power
consumption
•
STOP mode, where both low-speed oscillation and high-speed oscillation stop
•
Stop code acceptor function, which controls transition to STOP mode
•
Block control function, which power downs the circuits of unused function blocks (reset registers and stop
clock supplies)
4.1.2 Configuration
Figure 4-1 shows an operating state transition diagram.
Figure 4-1 Operating State Transition Diagram
System reset
mode
Reset or BRK
instruction
Release reset
Program run
mode
STOP mode
Reset
Reset
STP=”1”
External
Interrupt
HLT=”1”
DHLT=”1”
HLTH=”1”
Power on
HALT mode
DEEP-HALT mode
HALT-H mode
Interrupt
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...