ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–9
12.2.5 SIOF0 Baud Rate Register (SF0BRR)
Address: 0F786H
Access: R/W
Access size: 16 bits
Initial value: 5002H
7
6
5
4
3
2
1
0
-
SF0BR7
SF0BR6
SF0BR5
SF0BR4
SF0BR3
SF0BR2
SF0BR1
SF0BR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
-
SF0LAG1
SF0LAG0
SF0LEAD1
SF0LEAD0
–
–
SF0BR9
SF0BR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
1
0
1
0
0
0
0
SF0BRR is a special function register (SFR) used to set the operation mode.
Do not change the setting of this register during transfer. Operation is not guaranteed if it is changed during
transfer.
Description of Bits
•
SF0BR9-0
(bits 9 to 0)
Sets the baud rate (f
SCK
)(setting enabled in Master mode).
f
SCK
=f
HLSCLK
/(2×SF0BR9-0)
f
HLSCLK
: HSCLK or LSCLK frequency
SF0BR[9:0]
Description
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
2 dividing
0
0
0
0
0
0
0
0
0
1
2 dividing
0
0
0
0
0
0
0
0
1
0
4 dividing (initial value)
0
0
0
0
0
0
0
0
1
1
6 dividing
:
:
1
1
1
1
1
1
1
1
1
1
2046 dividing
[Note]
The maximum SSIOF transfer frequency is 4MHz. This setting should not exceed 4MHz.
If using P22 as SCKF0 in master mode, the max frequency is 2MHz.
•
SF0LEAD1-0
(bits 13 to 12)
SF0LEAD1-0 set the SSF0 –SCKF0 delay interval (setting enabled only in Master mode).
SF0LEAD1
SF0LEAD0
Description
0
0
0.5 X SCK
0
1
0.5 X SCK (initial value)
1
0
1.0 X SCK
1
1
1.5 X SCK
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...