ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–1
Table of Contents
Chapter 1
1. Overview ........................................................................................................................................... 1-1
1.1 Features
....................................................................................................................................... 1-1
1.2 Configuration of Functional Blocks
............................................................................................ 1-5
1.2.1 Block Diagram of ML620Q503/504 ............................................................................ 1-5
1.3 Pins .........................................................................................................................................
1-6
1.3.1 Pin Layout ................................................................................................................... 1-6
1.3.1.1 Pin Layout of ML620Q503/Q504 TQFP Package
............................................ 1-6
1.3.2 List of Pins .................................................................................................................. 1-7
1.3.2.1 List of Pins of ML620Q503/Q504 TQFP Package
........................................... 1-7
1.3.3 Description of Pins .................................................................................................... 1-10
1.3.4 Termination of Unused Pins ..................................................................................... 1-13
Chapter 2
2. CPU and Memory Space .................................................................................................................. 2-1
2.1
General
Description
....................................................................................................................
2-1
2.1.1
Features ...................................................................................................................... 2-1
2.1.2
Notes When Executing SB/RB Instruction .................................................................. 2-1
2.2
Program
Memory Space
.............................................................................................................
2-2
2.3
Data
Memory Space
...................................................................................................................
2-3
2.4
Instruction
Length
........................................................................................................................
2-5
2.5 Data Type ............................................................................................................................... 2-5
2.6
Description of Registers
.............................................................................................................
2-5
2.6.1
List of Registers .......................................................................................................... 2-5
2.6.2
Data Segment Register (DSR) ................................................................................... 2-5
2.7
Multiplication/Division Coprocessor
...........................................................................................
2-
6
2.7.1
General Description .................................................................................................... 2-6
2.7.2
List of Registers .......................................................................................................... 2-6
2.7.2.1 Registers A, B, C, and D (CR0 to CR7)
............................................................ 2-7
2.7.2.2
Operation Mode Register (CR8)
....................................................................... 2-8
2.7.2.3
Operation Status Register (CR9)
...................................................................... 2-9
2.7.2.4
Coprocessor ID Register (CR15)
.................................................................... 2-10
2.7.3
Description of Operation ........................................................................................... 2-11
Chapter 3
3. Reset Function .................................................................................................................................. 3-1
3.1
Overview
......................................................................................................................................
3-1
3.1.1
Features ...................................................................................................................... 3-1
3.1.2
Configuration ............................................................................................................... 3-1
3.1.3
List of Pin .................................................................................................................... 3-1
3.2
Description of Registers
.............................................................................................................
3-2
3.2.1
List of Registers .......................................................................................................... 3-2
3.2.2
Reset Status Register (RSTAT) .................................................................................. 3-3
3.3
Description of Operation
............................................................................................................. 3-4
3.3.1
Cause of Reset ........................................................................................................... 3-4
3.3.2
Operation of System Reset Mode ............................................................................... 3-4
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...