ML620Q503/Q504 User’s Manual
Chapter 26 Analog Comparator
FEUL620Q504 26–6
26.3 Function description
26.3.1 Comparator function
The Comparator has following 3 modes.
1.
Supervisor mode
: Suitable for voltage monitor always.
2.
Single mode
: Suitable for voltage monitor regularly. Generate interrupts par specified.
3.
Single monitor mode
: Suitable for voltage monitor regularly. Software outputs compare result
always.
26.3.2 Supervisor mode
This mode set comparator always on. And generate interrupt by variation of the compare result.
Without interrupt, compare result can be monitor by reading CMPnD bit from Software.
Setting instruction:
(1)
Set Operating clock, filtering, interrupt option, and supervisor mode by CMPnMOD register.
The operation of the CMPnTGO signal changes by this setting..
CMPnE1-0
Description
Interrupt
CMPnTGO signal
00
No interrupt
Asserted when CMPnD is ”1” when
starting measurement or CMPnD is
changed from “0” to ”1” during
measurement.
01
L interrupt : Generate interrupt when CMPnD
is ”0”
CMPnD is ”0” when starting measurement or
CMPnD is changed from “1” to ”0” during
measurement.
Asserted when CMPnD is ”0” when
starting measurement or CMPnD is
changed from “1” to ”0” during
measurement.
10
H interrupt : Generate interrupt when CMPnD
is ”1”
CMPnD is ”1” when starting measurement or
CMPnD is changed from “0” to ”1” during
measurement.
Asserted when CMPnD is ”1” when
starting measurement or CMPnD is
changed from “0” to ”1” during
measurement.
11
Both edge(L and H) interrupt
CMPnD is ”1” when starting measurement or
CMPnD is changed from “0” to ”1” or “1” to ”0”
during measurement.
(2) Set CMPnEN
In case of interrupt, generate interrupt only when the condition set by CMPnE1-0 match.
(3)After Trdy progress, CMPnRF becomes ”1”, and then CMPnD becomes valid;
In case of reading CMPnD with no interrupt or before generating interrupt, please make sure CMPnRF is ”1”.
Because status is stable waiting during CMPnRF is ”0” at operation, CMPnD value is invalid.
CMPnRF need to be “1” when switch to STOP mode.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...