Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–59
5.3.7 Flow Chart (When Interrupt Level Control Enabled)
The figure below shows the flow chart of the software processing of a maskable interrupt when the interrupt
level control is enabled. The EI and DI instructions allow the execution of multiple interrupts by a
higher-level maskable interrupt request during the "execution of the desired processing". Note that a
non-maskable interrupt can be made for a maskable interrupt regardless of the execution of EI and DI
instructions due to the specification of U16 processor.
Execute desired processing
Interrupt processing end
Restore return PC to PC and
pre-interrupt PSW to PSW
from stack
Write access to the
current interrupt level register
(CIL)
DI instruction: Disable interrupt
Save ELR1 (return PC) and
EPSW1 (pre-interrupt PSW) to stack
EI instruction: Enable interrupt
Maskable interrupt request
Save general-purpose
registers to memory
When not multiple When multiple
Maskable interrupt request
Execute desired processing
Interrupt processing end
Restore general-purpose
registers from memory
Save general-purpose
registers to memory
Restore general-purpose
registers from memory
RTI instruction
Write access to the
current interrupt level register
(CIL)