ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–43
5.2.21 External Interrupt 01 Selection Register (EXI01SEL)
Address: 0F048H
Access: R/W
Access size: 8/16 bit
Initial value: 0000H
7
6
5
4
3
2
1
0
EXI0SEL
EXI0S7
EXI0S6
EXI0S5
EXI0S4
EXI0S3
EXI0S2
EXI0S1
EXI0S0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
EXI1SEL
EXI1S7
EXI1S6
EXI1S5
EXI1S4
EXI1S3
EXI1S2
EXI1S1
EXI1S0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
EXI01SEL is a special function register (SFR) used to select the port used as EXI0/1.
Description of Bits
•
EXI0S3-0
(bits 3 to 0),
EXI0S7-4
(bits 7 to 4)
The EXI0S3-0 registers are used to select the bit of the port used as EXI0.
The EXI0S7-4 registers are used to select the group of the port used as EXI0 (Example: When EXI0S7:4
= "5" and EXI0S3:0 = "1", Port 51 is used as EXI0).
EXI0S7-4
EXI0S3-0
0
1
2
3
4
5
6
7
0
P00
P01
P02
P03
P04
P05
-
-
1
PXT0
PXT1
-
-
-
-
-
-
2
P20
P21
P22
P23
-
-
-
-
3
P30
P31
P32
P33
P34
P35
P36
P37
4
P40
P41
P42
P43
P44
P45
P46
P47
5
P50
P51
P52
P53
P54
P55
P56
P57
Setting other than above is prohibited.
•
EXI1S3-0
(bits 11 to 8),
EXI1S7-4
(bits 15 to 12)
The EXI1S3-0 registers are used to select the bit of the port used as EXI1.
The EXI1S7-4 registers are used to select the group of the port used as EXI1 (Example: When EXI1S7:4
= "5" and EXI1S3:0 = "1", Port 51 is used as EXI1).
EXI1S7-4
EXI1S3-0
0
1
2
3
4
5
6
7
0
P00
P01
P02
P03
P04
P05
-
-
1
PXT0
PXT1
-
-
-
-
-
-
2
P20
P21
P22
P23
-
-
-
-
3
P30
P31
P32
P33
P34
P35
P36
P37
4
P40
P41
P42
P43
P44
P45
P46
P47
5
P50
P51
P52
P53
P54
P55
P56
P57
Setting other than above is prohibited.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...