ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–17
9.2.10 FTMn Clock Register (FTnCLK : n=0,1,2,3)
Address: 0F40EH(FT0CLKL/FT0CLK), 0F40FH(FT0CLKH),
0F42EH(FT1CLKL/FT1CLK), 0F42FH(FT1CLKH),
0F44EH(FT2CLKL/FT2CLK), 0F44FH(FT2CLKH),
0F46EH(FT3CLKL/FT3CLK), 0F46FH(FT3CLKH)
Access: R/W
Access size: 8/16 bit
Initial value: 0000H
7
6
5
4
3
2
1
0
FTnCLKL
–
FTnCKD2
FTnCKD1
FTnCKD0
–
–
FTnCK1
FTnCK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
FTnCLKH
–
–
–
–
–
FTnXCK2
FTnXCK1
FTnXCK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
FTnCLK is a special function register (SFR) used to set the function of FTMn.
Description of Bits
•
FTnCK1-0
(bits 1 to 0)
Selects the timer clock source of FTMn.
FTnMD
FTnCK
Description
TIMER
CAPTURE
PWM1/2
0
LSCLK (initial value)
1
OSCLK
2
HSCLK
3
EXTCLK(Clock selected by FTnXCK2-0)
•
FTnCKD2-0
(bits 6 to 4)
Selects the dividing ratio of the timer clock source of FTMn.
FTnMD
FTnCKD
Description
TIMER
CAPTURE
PWM1/2
0
divide by 1 (initial value)
1
divide by 2
2
divide by 4
3
divide by 8
4
divide by 16
5
divide by 32
6
divide by 64
7
Reserved
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...