Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 6 Clock Generation Circuit
FEUL620Q504 6–16
6.3.1.6 Low-Speed External Clock Input Mode Operation
For the low-speed external clock, the oscillation start/stop can be controlled by the frequency control register 2
(FCON2).
If it sets the XTM0 and XTM1 bits of FCON2 to "11", external clock input becomes accepted and then the
external clock input is counted to 16, then the low-speed clock (LSCLK) switches to the external clock.
In this time, the low-speed oscillation clock switch interrupt(LOSCINT) is generated.
Refer to Chapter 4 “Power Management” for the operation at each power down mode.
Figure 6-8 Low-Speed Clock Generation Circuit Operation (External Clock Mode)
V
DD
RESET
External interrupt occurred
LSCLK switch
external 16 counts
LSCLK RC oscillation
STOP
mode
Built-in RC oscillation
LSCLK switch
RC oscillation 128counts
LOSCS bit
SYSCLK
High-speed clock
same as stop before
XTM1,0=”11”
RC oscillation 130 counts
LSCLKI
External clock External clock
extarnal 16 counts
Built-in RC oscillation
RC oscillation 29counts
LOSCINT
Low-speed
Built-in RC oscillation
External clock
RC oscillation
External clock