ML620Q503/Q504 User’s Manual
Chapter 26 Analog Comparator
FEUL620Q504 26–4
26.2.3 Comparator n mode Registers (CMPnMOD : n=0,1)
Address: 0F922H(CMP0MODL/CMP0MOD), 0F923H(CMP0MODH),
0F92AH(CMP1MODL/CMP1MOD), 0F92BH(CMP1MODH)
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7
6
5
4
3
2
1
0
CMPnMODL
–
–
CMPnMD1 CMPnMD0
–
–
CMPnE1
CMPnE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
CMPnMODH
–
–
–
CMPnCK
–
–
CMPnSM1 CMPnSM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
CMPnMOD is special function registers (SFRs) to set the function mode of Comparator n.
CMPnMOD needs to be set during CMPnEN is “0”.
Description of Bits
•
CMPnE1-0
(bits 1 to 0)
The CMPnE1-0 are used to set comparator judge interrupt generation condition. Each function mode has different
interrupt generation sources.
CMPnMD
CMPnE1
CMPnE0
Description
Single mode
0
*
Generate interrupt when CMPnD is ”0”
1
*
Generate interrupt when CMPnD is ”1”
Single monitor mode
*
*
Setting is invalid (Generate interrupt once measurement is
completed)
Supervisor mode
0
0
No interrupt
(
initial value
)
0
1
L interrupt : Generate interrupt when CMPnD is ”0”
CMPnD is ”0” when starting measurement or
CMPnD is changed from “1” to ”0” during measurement.
1
0
H interrupt : Generate interrupt when CMPnD is ”1”
CMPnD is ”1” when starting measurement or
CMPnD is changed from “0” to ”1” during measurement.
1
1
Both edge(L and H) interrupt
CMPnD is ”1” when starting measurement or
CMPnD is changed from “0” to ”1” or “1” to ”0” during
measurement.
[Note]
This setting affects CMPnTGO signal. Refer to 26.3.2 for details. Use the CMPnTGO signal in
Supervisor mode
.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...