ML620Q503/Q504 User's Manual
Chapter 2 CPU and Memory Space
FEUL620Q504 2–3
2.3 Data Memory Space
The data memory space consists of the segment 0 for the ROM window area, RAM area, and SFR area, the
segments 7 and F for the flash data area, and the segments 1, 8, and 9 for the ROM reference area.
The data memory space is configured by 32K words (64Kbytes) as one segment (data segment).
The ROM window area is a window opened in the ROM area for the ROM area data to be accessed using the
RAM addressing. The same address data in the program memory space can be read through this window.
In the SFR area, the special function registers (SFRs) that control the LSI function block operations are placed.
In the flash data area, the Flash memory is placed which is readable and writable as data area.
For writing to this area, see Chapter 27, "Flash Memory Control".
Note that the flash data area cannot be operated as program memory.
The data memory stores 8-bit data and is specified by 20 bits consisting of higher 4 bits as DSR and lower 16 bits
as addressing specified by each instruction.
Figure 2-3 shows the configuration of the data memory space.
[Note]
The contents of the RAM area are undefined at power-on and system reset. Initialization of this area by
software is required.
DSR:DADR
Data segment 0
Data segment 7
0:0000H
ROM Window
area
7:0000H
7:07FFH
Data flash
area
0:7DFFH
7:0800H
Unused area
0:7F00H
Unused area
0:E7FFH
0:E800H
0:EFFFH
RAM area
0:F000H
SFR area
0:FFFFH
7:FFFFH
8bit
8bit
DSR:DADR
Data segment 8
Data segment F
8:0000H
Code segment 0
Reference area
F:0000H
F:07FFH
Data segment 7
Reference area
F:0800H
Unused area
8:7FFFH
Unused area
8:FFFFH
F:FFFFH
8bit
8bit
* Segments 1 to 6 and 9 to E are unused areas.
(a) ML620Q503
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...