Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–35
5.2.16 Interrupt Level Control Register 5 (ILC5)
Address: 0F02CH
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7 6 5 4 3 2 1 0
ILC5L L1TM3 L0TM3 L1TM2 L0TM2 L1TM1 L0TM1 L1TM0 L0TM0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
ILC5H L1TM7 L0TM7 L1TM6 L0TM6 L1TM5 L0TM5 L1TM4 L0TM4
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
The interrupt level control register 5 is a special function register (SFR) used to set the level of the interrupt
source enabled by IE5.
Write access to this register is possible only when the interrupt level control is enabled by the ILEN register.
Level 1 to 4 can be set for each interrupt source. The register which has the higher level is given the higher
priority.
Description of Bits
•
L1-0TM0 (bits 1 to 0)
L1-0TM0 set the level of the 8-bit timer 0 interrupt (TM0INT).
L1TM0 L0TM0 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0TM1 (bits 3 to 2)
L1-0TM1 set the level of the 8-bit timer 1 interrupt (TM1INT).
L1TM1 L0TM1 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0TM2 (bits 5 to 4)
L1-0TM2 set the level of the 8-bit timer 2 interrupt (TM2INT).
L1TM2 L0TM2 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4