ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–55
A-2: When a subroutine is called by the program in executing an interrupt routine
A-2-1: When multiple interrupts are disabled
•Processing immediately after the start of interrupt routine execution
Specify the "PUSH LR" instruction to save the subroutine return address in the stack.
•Processing at the end of interrupt routine execution
Specify "POP LR" immediately before the RTI instruction to return from the interrupt processing
after returning the subroutine return address to LR.
A-2-2: When multiple interrupts are enabled
•Processing immediately after the start of interrupt routine execution
Specify "PUSH LR, ELR, EPSW" to save the interrupt return address, the subroutine return
address, and the EPSW status in the stack.
•Processing at the end of interrupt routine execution
Specify "POP PC, PSW, LR" instead of the RTI instruction to return the saved data of the interrupt
return address to PC, the saved data of EPSW to PSW, and the saved data of LR to LR.
Example of
description: Status
A-2-2
Intrpt_A-2-2:
; Start
PUSH
ELR,EPSW,LR
; Save ELR, EPSW, LR
at the beginning
EI
; Enable interrupt
:
Sub_1:
;
:
DI
; Disable interrupt
:
:
:
BL Sub_1
; Call subroutine Sub_1
:
:
RT
; Return PC from
LR
POP PC, PSW, LR
; Return PC from the stack
; End of subroutine
; Return PSW from the
stack
; Return LR from the stack
; End
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...