Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 11 Synchronous Serial Port (SSIO)
FEUL620Q504 11–6
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S0CK2-0 (bits 10 to 8)
The S0CK2-0 bits are used to select the transfer clock of the synchronous serial port. When the internal clock is
selected, this LSI is set to master mode and when the external clock is selected, it is set to slave mode.
S0CK2 S0CK1 S0CK0 Description
0 0 0
1/1 LSCLK (initial value)
0 0 1 1/2 LSCLK
0 1 0 1/4 OSCLK
0 1 1
1/8 OSCLK
1 0 0 1/16 OSCLK
1 0 1 1/32 OSCLK
1 1 0 External clock 0 (SCK0)
1 1 1
reserved
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S0CKT (bit 12)
The S0CKT bit is used to select a transfer clock output phase.
S0CKT Description
0
Clock type 0: Clock is output with a “H” level being the default. (Initial
value)
1 Clock type 1: Clock is output with a “L” level being the default.
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S0NEG (bit 13)
The S0NEG bit is used to select the positive or negative logic of the transfer clock output.
S0NEG Description
0
Positive logic (Initial value)
1 Negative logic
[Note]
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Do not change any of the SIO0MOD register settings during transmission/reception.
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SCK0 Max clock input frequency is 1/4 of SYSCLK or 2MHz at slave mode.
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SCK0 Max clock output frequency is 2MHz if using P02 as SCK0 in master mode.