Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-20
14.3.4 FIFO Mode
When the receive FIFO and reception interrupt are both enabled, reception interrupts are generated as follows:
(A)
If the number of characters present within the FIFO exceeds the programmed trigger level, a received data
read request interrupt is generated. This interrupt is immediately cleared when the number of characters
present within the FIFO drops below the trigger level.
(B) As with the received data read request interrupt, the UAnIIR received data read request display is set to "1"
if the number of characters present within the FIFO exceeds the trigger level, and cleared to "0" if it drops
below the trigger level.
(C) The received data error interrupt has a higher priority than the received data read request interrupt.
(D) The received data read request flag is set to "1" as soon as the data is transferred from the receive shift
register to the FIFO, and cleared to "0" when the FIFO becomes empty.
When the receive FIFO and the reception interrupt are both enabled, a character timeout interrupt is generated as
follows.
(A)
A character timeout interrupt is generated when the following conditions are met.
•
There is at least one character present in the FIFO.
•
An amount of time required to transfer at least 4 characters has elapsed since a character was last
received (if 2 stop bits are specified, the time after the first stop bit is calculated).
•
An amount of time required to transfer at least 4 characters has elapsed since the receive FIFO was last
read.
For example, if 1 start bit + 8 character bits + 1 parity bit + 2 stop bits is specified, and the transfer speed is
300 baud, the said amount of time will be approximately 160 ms.
(B) SYSCLK is used to calculate the character time.
(C) When a character is read out from the FIFO, the character timeout interrupt and the timer used for timeout
detection will be cleared.
(D) When no character timeout interrupt is generated, the timeout detection timer will be cleared when a
character is read out from the FIFO or a new character is received.
The transmission interrupt is generated as follows when the transmitter section and the transmit FIFO interrupts
have been enabled.
(A)
If the transmit FIFO is empty, a transmitted data write request interrupt occurs. This interrupt is cleared
when a character is written to the transmit FIFO or when UAnIIR is read out.
(B) When the following conditions are met, the transmitted data write request interrupt will be delayed for an
amount of time equivalent to "time required to transmit one character – time when last stop bit occurred".
•
There was a period when only one character was present in the FIFO after THRE (transmitted data write
request) was last set.
•
THRE was set.
[Note]
Transmit FIFO is an empty state, but there is the case that all transmit processing doesn’t complete.
Confirm that transmit shift register (TSR) became empty in UF0TEMT bit of UAF0LSR register before
stopping high-speed clock (Transition to modes such as STOP / DEEP-HALT / HALT-H).