ML620Q503/Q504 User’s Manual
Chapter 7 Time Base Counter
FEUL620Q504 7–4
7.2.3 Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJ)
Address: 0F062H
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7
6
5
4
3
2
1
0
LTBADJL
LADJ7
LADJ6
LADJ5
LADJ4
LADJ3
LADJ2
LADJ1
LADJ0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
LTBADJH
–
–
–
–
–
LADJ10
LADJ9
LADJ8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
LTBADJL and LTBADJH are special function registers (SFRs) to set the frequency adjustment values of the low-speed
time base clock.
Description of Bits
•
LADJ10-0
(bits 10 to 0)
The LADJ10-0 bits are used to adjust frequency.
Adjustment range:
Approx.
−
488ppm to +488ppm.
Adjustment accuracy:
Approx. 0.48ppm
Frequency adjustment (Adjustment range: Approx.
−
488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm)
is possible for outputs of T8KHZ to T1HZ of LTBC by using the low-speed time base counter frequency adjust
registers (LTBADJH and LTBADJL).
Table7-1 shows correspondence between the frequency adjustment values (LTBADJH, LTBADJL) and adjustment
ratio.
Table 7-1 Correspondence between Frequency Adjustment Values (LTBADJH, LTBADJL)
and Adjustment Ratio
LADJ10 to 0
Hexadecimal Frequency adjustment ratio (ppm)
0
1
1
1
1
1
1
1
1
1
1
3FFH
+487.80
0
1
1
1
1
1
1
1
1
1
0
3FEH
+487.33
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
1
003H
+1.43
0
0
0
0
0
0
0
0
0
1
0
002H
+0.95
0
0
0
0
0
0
0
0
0
0
1
001H
+0.48
0
0
0
0
0
0
0
0
0
0
0
000H
0
1
1
1
1
1
1
1
1
1
1
1
7FFH
−
0.48
1
1
1
1
1
1
1
1
1
1
0
7FEH
−
0.95
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
0
0
0
0
1
401H
−
487.80
1
0
0
0
0
0
0
0
0
0
0
400H
−
488.28
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...