ML620Q503/Q504 User's Manual
Chapter 11 Synchronous Serial Port (SSIO)
FEUL620Q504 11–7
11.3 Description of Operation
11.3.1 Transmit Operation
When “1” is written to the S0MD1 bit and “0” is written to the S0MD0 bit of the serial mode register (SIO0MOD), this
LSI is set to a transmit mode.
When transmit data is written to the serial port transmit/receive buffer (SIO0BUF) and the S0EN bit of the serial port
control register (SIO0CON) is set to “1”, transmission starts. When transmission of 8/16-bit data terminates, a
synchronous serial port interrupt (SIO0INT) occurs and the S0EN bit is set to “0”.
Transmit data is output from SOUT0 pin.
When an internal clock is selected in the serial port mode register (SIO0MOD), the LSI is set to a master mode and
when an external clock (SCK0) is selected, the LSI is set to a slave mode.
The serial port mode register (SIO0MOD) enables selection of MSB first/LSB first.
The transmit data output pin (SOUT0) and transfer clock input/output pin (SCK0) must be set to the tertiary functions.
Figures 11-2, 11-3, 11-4 and 11-5 show the transmit operation waveforms of the synchronous serial ports for “clock type
0 and positive-logic”, “clock type 0 and negative-logic”, “clock type 1 and positive-logic” and “clock type 1 and
negative-logic”, respectively (8-bit length, LSB first).
Figure 11-2 Transmit Operation Waveforms of Synchronous Serial Port
for Clock Type 0 (8-bit Length, LSB first, Positive Logic)
Figure 11-3 Transmit Operation Waveforms of Synchronous Serial Port
for Clock Type 0 (8-bit Length, LSB first, Negative Logic)
S0EN
0
1
2
3
4
5
7
6
Transmit data
SCK0
SIO0TRL
SOUT0
SIO0INT
S0EN
0
1
2
3
4
5
7
6
Transmit data
SCK0
SIO0TRL
SOUT0
SIO0INT
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...