Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 18 Port 1
FEUL620Q504 18–6
18.3 Description of Operation
18.3.1 Input/Output Port Function
For each pin of Port 1, either output or input is selected by setting the Port 1 direction register (P1DIR).
In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode,
or CMOS output mode can be selected by setting the Port 1 control registers 0 and 1 (P1CON0 and P1CON1).
In input mode, high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor
can be selected by setting the Port 1 control registers 0 and 1 (P1CON0 and P1CON1).
At a system reset, high-impedance output mode is selected as the initial state.
In output mode, “L” or “H” level is output to each pin of Port 1 depending on the value set by the Port 1 data register
(P1D).
In input mode, the input level of each pin of Port 1 can be read from the Port 1 data register (P1D).
18.3.2 Other Function
A high-speed crystal/ceramic oscillation pin or an external clock input pin is assigned to Port 1 as a secondary function.
Select high-speed crystal/ceramic oscillation mode or external clock input mode by using the high-speed clock mode
select function of the OSCM1 and 0 bits of the frequency control register 0 (FCON0). In crystal/ceramic oscillation
mode, both P10 and P11 pins are used as the pins for crystal/ceramic oscillation.
In external clock input mode, the P11 pin is used as the input pin of external clock.