ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-13
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UF0TEMT
(bit 6)
UF0TEMT is set to "1" when both THR and the shift register for transmission (TSR) are empty. When a
character is loaded into THR, this bit is cleared to "0" and remains "0" until the character is transferred
from TXDF0. This bit is not cleared to "0" by reading UAF0LSR.
In FIFO mode, this bit is set to "1" when both the transmit FIFO and the shift register are empty.
UF0TEMT
Description
0
Transmitted data remains in either THR or TSR
1
Both THR and TSR are empty (initial value)
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UF0RFE
(bit 7)
UF0RFE is always 0 when FIFO is disabled. In the FIFO enable, this bit is set to "1" if any of parity,
framing, and break interrupt data errors exists within FIFO. This bit will be cleared when the data
causing the error is read out from the RBR, or when the data causing the error is cleared by
the FIFO
clear and then reading out the UAF0LSR.
UF0RFE
Description
0
No data error in FIFO mode (initial value)
1
A parity error, framing error, or break interrupt occurred in FIFO mode
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...