ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-15
Figure 4-5 Operation Waveforms in STOP Mode When CPU Operates with Low-Speed Clock
4.3.2.2 Oscillation Stop and Restart Timing of High-Speed Clock
When the STP bit of SBYCON is set to “1” with the stop code acceptor enabled while the high-speed clock is
operating, the mode changes to the STOP mode and the high-speed oscillation and low-speed oscillation stop.
When an external pin interrupt request that is interrupt-enabled (the interrupt enable flag is “1”) is issued, the
STP bit is set to “0”, and the high-speed oscillation and low-speed oscillation restart.
After generating interrupt request, low-speed built-in RC oscillation begins oscillating independently of the clock
mode. And, the clock is supplied as LSCLK after counts 29. And the counts 512, as OSCLK clock supply after
the high-speed built-in RC oscillation starts oscillation.
In the case of high-speed crystal/ceramic oscillation mode, oscillation is started after high-speed oscillation start
time (T
XTH
) from LSCLK supply. And, OSCLK changes from RC oscillation into crystal oscillation by the
automatic operation after counts 4096 by the crystal oscillation.
In the case of high-speed external clock mode, OSCLK changes from RC oscillation into external clock by the
automatic operation after counts 128 by the external clock from LSCLK supply.
For the high-speed oscillation start time (T
XTH
) and low-speed oscillation start time (T
XTL
), see the “Electrical
Characteristics” Section in Appendix C.
Figure 4-6 shows the operation waveforms in STOP mode when CPU operates with the high-speed clock.
Low-speed RC
oscillation
Oscillation
waveform
SYSCLK
SBYCON.STP bit
LSCLK
crystal
RC
OSCLK
program operational mode
STOP mode
program operational mode
Interrupt request
29 counts
Oscillation
waveform
T
XTL
Low-speed
crystal oscillation
8192 counts
crystal oscillation
RC oscillation
High-speed RC
oscillation
Oscillation waveform
512 counts
Oscillation waveform
T
XTH
High-speed
crystal oscillation
4096 counts
crystal
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...