ML620Q503/Q504 User's Manual
Chapter 13 UART
FEUL620Q504
13–7
•
U0PT1-0
(bits 11 to 10)
The U0PT1-0 bits are used to select "even parity", "odd parity", or "no parity" in the communication of
the UART.
U0PT1
U0PT0
Description
0
0
Even parity (initial value)
0
1
Odd parity
1
*
No parity bit
•
U0STP
(bit 12)
The U0STP bit is used to select the stop bit length in the communication of the UART.
U0STP
Description
0
1 stop bit (initial value)
1
2 stop bit
•
U0NEG
(bit 13)
The U0NEG bit is used to select positive logic or negative logic in the communication of the UART.
U0NEG
Description
0
Positive logic (initial value)
1
Negative logic
•
U0DIR
(bit 14)
The U0DIR bit is used to select LSB first or MSB first in the communication of the UART.
U0DIR
Description
0
LSB first (initial value)
1
MSB first
[Note]
Always set UA0MOD while communication is stopped, and do not rewrite it during communication.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...