ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-3
4.2.2 Stop Code Acceptor (STPACP)
Address: 0F008H
Access: W
Access size: 8 bits
Initial value: -(Undefined)
7
6
5
4
3
2
1
0
STPACP
–
–
–
–
–
–
–
–
R/W
W
W
W
W
W
W
W
W
Initial value
-
-
-
-
-
-
-
-
STPACP is a write-only special function register (SFR) that is used for setting a STOP mode.
When STPACP is read, “00H” is read.
When data is written to STPACP in the order of “5nH” and “0AnH” (where n is 0 to 0FH), the stop code
acceptor is enabled. When the STP bit of the standby control register (SBYCON) is set to “1” in this state, the
mode is changed to the STOP mode. When the STOP mode is set, the STOP code acceptor is disabled.
When another instruction is executed between the instruction that writes “5nH” to STPACP and the instruction
that writes “0AnH”, the stop code acceptor is enabled after “0AnH” is written. Note that, if data other than
“0AnH” is written to STPACP after “5nH” is written, the “5nH” writing process becomes invalid and “5nH”
should be written again.
During a system reset, the stop code acceptor is disabled.
[Note]
•The STOP code acceptor cannot be enabled on the condition that any interrupt enable flag and the
corresponding interrupt request flag are both “1” (for example, an interrupt request occurs when the MIE flag
is ”0”).
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...