Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

Page: 168 / 553

ML620Q503/Q504 User’s Manual
Chapter 7 Time Base Counter
FEUL620Q504 7–7
7.3 Description of Operation
7.3.1 Low-Speed Time Base Counter
The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset.
Three of LBC interrupt request interrupt by falling edge of clock output which was assigned by the low-speed time base
counter interrupt select register.
The output data of T128HZ to T1HZ of LTBC can be read from the low-speed time base counter register (LTBR).
When reading the data, read LTBR twice and check that the two values coincide to prevent reading of undefined data
during counting.
Figure 7-2 shows an example of program to read LTBR.
LEA offset LTBR ; EA
←
LTBR address
MARK:
L R0, [EA] ; 1st read
L R1, [EA] ; 2nd read
;
CMP R0, R1 ; Comparison for LTBR
BNE MARK ; To MARK when the values do not coincide
;
:
Figure 7-2 Programming Example for Reading LTBR
LTBR is reset when write operation is performed and the T128HZ to T1HZ outputs are set to “0”. At this time, Interrupt
occurs when clock is assigned to LTBC interrupt changing from “1” to “0”. Therefore, when LTBR is reset, After
prohibits each TBC interrupts of interrupt controller, LTBR is reset and the processing which clears LTBR interrupt
request which occurred by reset is needed. Figure 7-3 shows the sequence to clear the LTBC interrupt request.
Figure 7-3 Sequence to Clear the LTBC Interrupt Request which Occurred by LTBR Reset
1CPU cycle is needed after LTBR interrupt occurs until LTBC interrupt request flag of interrupt controller is set. When
LTBC interrupt request is cleared after the writing LTBR, Please do not put the order to clear request flag just after an
order to write in LTBR at. Please clear request flag after placing NOP, and putting time.
All LTBC interrupt is prohibited
(ELTBC0,1,2 bits of IE7 register is set to “0”)
Low-speed time base counter
is reset
(Write access to LTBR)
ALL LTBC interrupt request is clears
(QLTBC0,1,2 bits of IRQ7 register is set to “0”)
NOP
ALL LTBC interrupts is permitted
(ELTBC0,1,2 bits of IE7 register is set to “1”)