Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 6 Clock Generation Circuit
FEUL620Q504 6–1
6 Clock Generation Circuit
6.1 General Description
The clock generation circuit generates and provides the low-speed clock (LSCLK), the high-speed clock
(HSCLK), the system clock (SYSCLK), and the high-speed output clock (OUTCLK). LSCLK and HSCLK are
time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU, and OUTCLK is a clock
that is output from a port.
For the OUTCLK output port, see Chapter 21, "Port 4", Chapter 22, "Port 5".
For the STOP mode described in this chapter, see Chapter 4, "Power Management".
6.1.1 Features
•
Low-speed clock generation circuit:
- Crystal oscillation mode
- Built-in RC oscillation mode
- External clock input mode
- Interrupt generation at low-speed clock mode shift
•
High-speed clock generation circuit:
- Crystal/ceramic oscillation mode
- Built-in RC oscillation mode
- External clock input mode
6.1.2 Configuration
Figure 6-1 shows the configuration of the clock generation circuit.
FCON0 : Frequency control register 0
FCON1 : Frequency control register 1
FCON2 : Frequency control register 2
FSTAT : Frequency status register
Figure 6-1 Configuration of Clock Generation Circuit
PXT0I
/
XT
0
PXT1/
XT1/LSCLKI
P10/OSC0
P11/OSC1/
CLKIN
Low-speed clock
(LSCLK)
High-speed
clock (HSCLK)
System clock
(SYSCLK)
FCON0/1/2
Data bus
Dividing selection
1/1,1/2,1/4,1/8,
1/16,1/32
High-speed
output clock
(OUTCLK)
Low-speed clock
control circuit
FSTAT
RC
XT
Dividing selection
1/1,1/2,1/4,
1/8,1/16,1/32
High-speed clock control circuit
RC
XT
High-speed
source
oscillation clock
(OSCLK)
Timer clock
LOSCINT