ML620Q503/Q504 User's Manual
Chapter 28 Voltage Level Supervisor
FEUL620Q504 28-8
28.3.1 Supervisor mode
When setting ENVLS with VLSAMD1-0 set to ”10” or ”11”, the supervisor mode is activated.
The supervisor mode is useful for using the low voltage detection interrupt/reset with always-ON. The detection
flag(VLSF)/reset is masked until the ready flag is asserted.
If VLS interrupt is used, set the VLS interrupt before setting ENVLS.
VLSRF (ready flag) is asserted when T16KHZ 4
φ
(+2
φ
when the sampling is enabled) passes after setting
ENVLS. The software should read the VLSF value after VLSRF=”1”.
Even if the VLS interrupt or VLS reset is allowed, the issue is allowed after VLSRF is asserted.
When V
DD
becomes lower than the specified threshold voltage, a VLS interrupt or VLS reset is issued.
To turn off the VLS function, set ENVLS to ”0” from the software.
Figure 28-2 shows an example of the operation timing diagram when detecting without sampling and setting the
VLS reset issue.
①
Set ENVLS to “1” from the CPU to turn on the VLS.
②
When the VLS analog output is stabilized, the ready flag (VLSRF) is set to ”1”.
③
The voltage level detection flag (VLSF) is set to “1” to issue a VLS reset because V
DD
becomes
lower than the specified threshold voltage (V
VLS
).
④
The voltage level detection flag (VLSF) is set to “0” to release the VLS is reset because V
DD
becomes higher than the specified threshold voltage (V
VLS
+H
VLS
).
⑤
Set ENVLS to “0” from the CPU to turn off the VLS.
Figure 28-2 Operation Timing Diagram When Detecting without Sampling and Setting VLS Reset
Issue
↓
Stabilization
time
ENVLS
Threshold voltage
V
VLS
VLS analog output
V
SS
V
DD
Ready flag: VLSRF
↓
↓
↓
↓
Detection flag: VLSF
VLS reset
(rise)
(fall)
V
VLS
+H
VLS
①
②
③
④
⑤
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...