Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 16 Port XT
FEUL620Q504 16–5
16.3 Description of Operation
16.3.1 Input Port Function
In the initial state after system reset, input is disabled for both the pins of the port XT.
When the pins of the port XT are set to the input state by the port XT direction register (PXTDIR), their input
level can be read by reading the port XT data register (PXTD).
16.3.2 Primary Function Other Than Input Port
The low-speed crystal oscillation pin, external clock input pin, or external interrupt is assigned to the port XT as
the primary function other than the input port.
When the XTM1 and XTM0 bits of the frequency control register 0 (FCON2) are set to the crystal oscillation
mode, the low-speed crystal oscillation mode or the external clock input mode is selected.
In the low-speed crystal oscillation mode, both the PXT0 and PXT1 pins are used as the pins for crystal
oscillation.
In the external clock input mode, the PXT1 pin is used as the input pin of the external clock. In this case, the
PXT0 pin is in the input-disabled state.
To use the port XT as the low-speed crystal oscillation pin or the external clock input pin, set the appropriate port
to the input port disabled state.
To use the port XT as the external interrupt input (EXII0 to EXII1), set the appropriate port to the input port
enabled state, and configure the setting to use the port as the external interrupt with the external interrupt mode
register (EXI01SEL).
PXTDIR
setting
FCON2
setting
PXT0 pin PXT1 pin
Crystal
oscillation
0 1 Crystal
oscillation
Crystal oscillation
External
clock
0 3 Input disabled External clock
input
Input port/
External
Interrupt
1 2 General-purpose
input pin/
External
Interrupt
General-purpose
input pin/
External Interrupt